Wafer-Level BGA MOS Capacitor 100 pF 30V Micro-Bump Ready Flip-Chip Chip for Bondwire-Free RF Assembly

HFC101S30V100 Wafer-Level BGA MOS Capacitor — 100 pF 30V Flip-Chip Ready

In short: The HFC101S30V100 is a 100 pF, 30 V single-layer MOS capacitor built on high-resistivity float-zone silicon with a thermally grown SiO2 dielectric. It is supplied with wafer-level micro-bump (BGA) termination for flip-chip, bondwire-free assembly, and its amorphous SiO2 dielectric architecture does not exhibit dipole fatigue. It is used for DC blocking, RF bypass and coupling in dense RF and power modules. Custom capacitance values, bump pitches and chip geometries are available.

Key Facts

Wafer-Level BGA / Micro-Bump Ready

The device is delivered with wafer-level under-bump metallization (UBM) and a copper-pillar micro-bump with a SnAg solder cap, so it can be placed directly by standard flip-chip bonders and processed in wafer-level packaging (WLP) and BGA reflow lines. Every die receives wafer-level electrical test, and a digital wafer map is available for traceability.

• Copper-pillar micro-bump with SnAg solder cap, 80 µm pitch (custom pitch available)
• Reflow compatible up to 260 °C peak; moisture sensitivity level MSL 1
• 100% wafer-level electrical test with digital wafer map

Flip-Chip Ready for Bondwire-Free Assembly

Because both terminals are placed on one face through symmetric bump metallization, the capacitor can be attached directly to laminate, ceramic or silicon interposers without gold wire bonds. Removing bond wires removes the interconnect that normally dominates series inductance, and also removes the wire-bond heel fatigue failure mode. This suits designs that need short, repeatable RF return paths and a low, stable interconnect inductance.

• No gold wire bonds required
• Intrinsic chip ESL <0.05 nH; series resonance >6 GHz
• Compatible with C4 and copper-pillar flip-chip bonders

Applications

• Wafer-level RF front-end modules and phased-array beamformer tiles
• Flip-chip DC blocks and RF coupling in hybrid microcircuits
• Bias network decoupling for RF power amplifiers
• High-density bypass in multi-chip modules
• 5G small-cell and backhaul radio front-ends
• Test and measurement front-ends requiring low, stable ESL