products details

Created with Pixso. Home Created with Pixso. Products Created with Pixso.
MOS Capacitors
Created with Pixso.

Wide-Temperature 1000 pF Single Layer MOS Capacitor Low Outgassing Chip for Aerospace Defense Electronics

Wide-Temperature 1000 pF Single Layer MOS Capacitor Low Outgassing Chip for Aerospace Defense Electronics

Brand Name: Hoan
Model Number: HACC102S100V500
MOQ: 10 Pieces
Payment Terms: T/T,L/C,D/A,D/P
Detail Information
Place of Origin:
Shaanxi, China
Certification:
ISO 9001:2015, RoHS 2015/863, ASTM E595 Outgassing Tested
Mounting Type:
Wire Bondable / AuSn Eutectic, Conductive Epoxy Or Sintered Silver
Wire Bond Pull Strength:
>6 Gf For 25 µm Au Wire (MIL-STD-883 Method 2011.7)
ESD Rating:
Class 0 (HBM) Per JESD22-A114
Moisture Sensitivity:
MSL 1 Per J-STD-020
Highlight:

1000 pF MOS capacitor aerospace

,

single layer MOS capacitor low outgassing

,

wide-temperature MOS capacitor defense electronics

Product Description

HACC102S100V500 Wide-Temperature 1000 pF 100V Single Layer MOS Capacitor Chip

Short answer: the HACC102S100V500 is a single layer MOS capacitor with 1000 pF ±10% capacitance and a 100V DC rating, built on float-zone silicon with a 300 nm thermally grown SiO2 dielectric in a 0.50 x 0.50 x 0.15 mm chip. It is specified for wide-temperature, low-outgassing assemblies that are die attached and wire bonded. Capacitance, voltage rating, chip geometry, dielectric type and metallization stack are all customizable.


Specifications at a Glance

Parameter Value
Capacitance 1000 pF ±10% (±5% available)
Rated DC voltage 100V
Dielectric Thermal SiO2, 300 nm
Chip size 0.50 x 0.50 x 0.15 mm
Q factor >2000 at 1 MHz, >200 at 1 GHz
ESR at 1 GHz <0.1 Ω
Intrinsic ESL <0.05 nH
TCC 0 ±30 ppm/°C
Leakage <10 nA at 25°C, <100 nA at 125°C
Outgassing TML <0.60%, CVCM <0.05% per ASTM E595
Top electrode TaN/TiW/Ni/Au, ≥2.5 µm Au, wire bondable
Operating temperature -65°C to +200°C extended-range build
MSL MSL 1 per J-STD-020


Wide-Temperature Stability for Aerospace and Defense Electronics

Thermal SiO2 is paraelectric, so the capacitance stays where the designer put it. Temperature coefficient is 0 ±30 ppm/°C across the -55°C to +125°C range, DC bias coefficient is below 10 ppm/V from 0V to the full 100V rating, and there is no ferroelectric aging, so long service life does not mean silent value drift. The extended-range build is tested from -65°C to +200°C with a qualification report per lot on request, and 1000 thermal cycles between -65°C and +150°C produce no electrode delamination. Typical use is avionics, satellite bus power distribution, radar front-ends, high-temperature industrial controls and down-hole instrumentation.


Semiconductor-Grade Purity and Low Outgassing for Ultra-Clean Applications

Because the dielectric is thermally grown in a wafer fab instead of being deposited from a ceramic slurry, the finished chip contains no binder, sintering aid or residual organic vehicle. Total mass loss is under 0.60% and collected volatile condensable materials under 0.05% per ASTM E595, well inside the screening limits applied to vacuum-exposed hardware. That matters anywhere a condensed film would fog an optical surface or contaminate a detector: vacuum instrument chambers, electron and ion beam columns, mass spectrometer optics, sealed sensor packages and satellite payload assemblies. Wafer lot traceability and, on request, residual gas analysis data ship with each lot.


Typical Applications

  • Satellite bus power distribution and payload DC blocking
  • Phased-array transmit/receive module supply decoupling
  • Radar front-end matching networks from X-band to Ka-band
  • Avionics and engine control electronics at elevated temperature
  • Vacuum instrumentation, ion optics and mass spectrometer front-ends
  • Down-hole and geothermal instrumentation
  • GaN-on-SiC HEMT drain bias decoupling (28-50V supply)



Wide-Temperature 1000 pF Single Layer MOS Capacitor Low Outgassing Chip for Aerospace Defense Electronics