Deep Level Trap Passivated MOS Capacitor HACC102S30V470 470pF 30V Zero C-V Hysteresis SLC

Deep Level Trap Passivated MOS Capacitor HACC102S30V470 470pF 30V

Summary: The HACC102S30V470 is a 470 pF ±10%, 30 V DC single-layer MOS capacitor with a deep-level trap passivated Si/SiO₂ interface. It is intended for RF matching, filtering and precision analog circuits where interface trap density, C-V hysteresis and long-term charge trapping affect stability.

Overview

The HACC102S30V470 is built on a float-zone silicon substrate (above 1000 Ω·cm) with a 300 nm thermal SiO₂ dielectric and a hydrogen / forming-gas passivation anneal. The chip measures 0.50 × 0.50 × 0.15 mm with 2.5 µm minimum gold top metallization. It supports wire bonding and eutectic die attach.

Key Features

• Deep-level trap passivation: D_it typically below 5 × 10¹⁰ cm^-2 eV^-1.
• Zero C-V hysteresis: below 10 mV between up and down sweeps.
• Charge trap elimination: low dielectric absorption and no DC bias derating.
• 470 pF ±10% at 30 V DC with a near-linear TCC of +35 ppm/°C.
• Single-layer construction with intrinsic ESL below 0.05 nH.
• ISO 9001:2015 and RoHS compliant, wire bondable gold metallization.
• Custom capacitance values available on the same 0.50 mm platform.

Electrical Specifications (T = 25°C unless noted)

Typical Applications

• Precision RF impedance matching and filter networks
• Stable DC blocking in analog and mixed-signal front ends
• VCO and reference circuits that require hysteresis-free tuning
• Sample-and-hold and precision integrator stages
• High-reliability industrial and instrumentation assemblies