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Radiation-Hardened MOS Capacitors 50V Single Layer 100 pF Capacitor Chip for Space Satellite Systems

Radiation-Hardened MOS Capacitors 50V Single Layer 100 pF Capacitor Chip for Space Satellite Systems

Brand Name: Hoan
Model Number: HACC101S50V100
MOQ: 10 Pieces
Payment Terms: L/C,D/A,D/P,T/T
Detail Information
Place of Origin:
Shaanxi, China
Certification:
ISO 9001:2015, RoHS
Wire Bond Pull Strength:
>6 Gf (25 Um Au Wire)
Operating Temperature:
-55 C To +125 C
Storage Temperature:
-65 C To +150 C
Chip Dimensions:
0.50 X 0.50 X 0.15 Mm (20 X 20 X 6 Mil)
RoHS:
Compliant (EU 2015/863)
Customization Options:
Capacitance 10-1000 PF, Tolerance +/-5%, Rectangular Die Up To 4:1, Bordered Electrode, Floating Backside, Custom Metallization
Highlight:

Radiation-Hardened MOS Capacitors 50V

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Single Layer 100 pF Capacitor Chip

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MOS Capacitors for Space Satellite Systems

Product Description

Radiation-Hardened MOS Capacitor HACC101S50V100 — 100 pF 50 V Single Layer Chip for Space and Satellite Systems

Product definition: The HACC101S50V100 is a radiation-hardened single-layer metal-oxide-semiconductor (MOS) capacitor with 100 pF ±10% capacitance and a 50 V DC rating. It is built on high-resistivity float-zone silicon (>1000 Ω·cm) with a 300 nm thermal SiO2 dielectric and a TiW-Au top / TiW-Pt-Au backside metallization system, in a 0.50 × 0.50 × 0.15 mm wire-bondable chip. It is designed for space, satellite, and other radiation-exposed RF and analog circuits that also require low phase noise and accurate simulation models.


At a Glance

  • Capacitance: 100 pF ±10% (±5% tolerance available)
  • Rated DC voltage: 50 V
  • Total ionizing dose: >100 krad(Si), ESCC 22900 test standard
  • Intrinsic chip ESL: <0.05 nH
  • Dielectric: thermal SiO2, 300 nm, amorphous (no piezoelectric response)
  • Chip size: 0.50 × 0.50 × 0.15 mm, wire-bondable / eutectic die attach


Specifications (T = 25 °C unless noted)

Parameter Value Condition
Capacitance 100 pF ±10% (±5% available) 1 MHz, 1.0 Vrms
Rated DC Voltage 50 V Continuous
Dielectric Withstanding Voltage >125 V DC (250% rated) 1 min, 25 °C
Dielectric Type Thermal SiO2, 300 nm, amorphous —
Substrate Float-zone Si, >1000 Ω·cm —
Intrinsic Chip ESL <0.05 nH De-embedded
Q Factor >2000 @ 1 MHz / >300 @ 1 GHz Typical
ESR @ 1 GHz <0.1 Ω Typical
Dissipation Factor ≤2.5% @ 1 MHz 1.0 Vrms
Insulation Resistance ≥104 MΩ At rated voltage
TCC 0 ±30 ppm/°C −55 °C to +125 °C
Leakage Current <10 nA @ 25 °C / <100 nA @ 125 °C At 50 V DC
ESD Class Class 0 HBM (JESD22-A114) —
Moisture Sensitivity MSL 1 (J-STD-020, unlimited floor life) —
TID Hardness >100 krad(Si) ESCC 22900
SEE Immunity No latch-up path, no SEU-sensitive node —
Operating Temperature −55 °C to +125 °C —
Storage Temperature −65 °C to +150 °C —
Top Metallization TiW-Au, ≥2.5 µm Au —
Backside Metallization TiW-Pt-Au, ≥1.0 µm Au (Pt barrier) —
Mounting Type Wire bondable / AuSn eutectic or conductive epoxy die attach —
Wire Bond Pull Strength >6 gf (25 µm Au wire) —
Chip Dimensions 0.50 × 0.50 × 0.15 mm (20 × 20 × 6 mil) —
RoHS Compliant (EU 2015/863) —


Typical Applications

  • Satellite transponder, TT&C and payload DC-blocking / bypass networks
  • Spacecraft oscillator (VCO) tank circuits and PLL loop filters
  • Phased-array module bias decoupling in radiation environments
  • Low-phase-noise synthesizer and reference chains
  • Aerospace and high-reliability RF front-ends that require validated simulation models


Radiation-Hardened MOS Capacitors 50V Single Layer 100 pF Capacitor Chip for Space Satellite Systems