| Brand Name: | Hoan |
| Model Number: | HACC101S50V100 |
| MOQ: | 10 Pieces |
| Payment Terms: | L/C,D/A,D/P,T/T |
Product definition: The HACC101S50V100 is a radiation-hardened single-layer metal-oxide-semiconductor (MOS) capacitor with 100 pF ±10% capacitance and a 50 V DC rating. It is built on high-resistivity float-zone silicon (>1000 Ω·cm) with a 300 nm thermal SiO2 dielectric and a TiW-Au top / TiW-Pt-Au backside metallization system, in a 0.50 × 0.50 × 0.15 mm wire-bondable chip. It is designed for space, satellite, and other radiation-exposed RF and analog circuits that also require low phase noise and accurate simulation models.
| Parameter | Value | Condition |
| Capacitance | 100 pF ±10% (±5% available) | 1 MHz, 1.0 Vrms |
| Rated DC Voltage | 50 V | Continuous |
| Dielectric Withstanding Voltage | >125 V DC (250% rated) | 1 min, 25 °C |
| Dielectric Type | Thermal SiO2, 300 nm, amorphous | — |
| Substrate | Float-zone Si, >1000 Ω·cm | — |
| Intrinsic Chip ESL | <0.05 nH | De-embedded |
| Q Factor | >2000 @ 1 MHz / >300 @ 1 GHz | Typical |
| ESR @ 1 GHz | <0.1 Ω | Typical |
| Dissipation Factor | ≤2.5% @ 1 MHz | 1.0 Vrms |
| Insulation Resistance | ≥104 MΩ | At rated voltage |
| TCC | 0 ±30 ppm/°C | −55 °C to +125 °C |
| Leakage Current | <10 nA @ 25 °C / <100 nA @ 125 °C | At 50 V DC |
| ESD Class | Class 0 HBM (JESD22-A114) | — |
| Moisture Sensitivity | MSL 1 (J-STD-020, unlimited floor life) | — |
| TID Hardness | >100 krad(Si) | ESCC 22900 |
| SEE Immunity | No latch-up path, no SEU-sensitive node | — |
| Operating Temperature | −55 °C to +125 °C | — |
| Storage Temperature | −65 °C to +150 °C | — |
| Top Metallization | TiW-Au, ≥2.5 µm Au | — |
| Backside Metallization | TiW-Pt-Au, ≥1.0 µm Au (Pt barrier) | — |
| Mounting Type | Wire bondable / AuSn eutectic or conductive epoxy die attach | — |
| Wire Bond Pull Strength | >6 gf (25 µm Au wire) | — |
| Chip Dimensions | 0.50 × 0.50 × 0.15 mm (20 × 20 × 6 mil) | — |
| RoHS | Compliant (EU 2015/863) | — |
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