HACC151S25V550 MOS Capacitors 150 pF 25V Q Factor 3000 Low TCC Wire Bondable Single Layer Die

Photo: HACC151S25V550 single layer MOS capacitor die, 0.55 mm square, gold top pad and gold backside plane

HACC151S25V550

150 pF MOS Capacitor, 25 V, Q Factor 3000 at 1 MHz, Wire Bondable Single Layer Die

Single layer MOS (metal-oxide-semiconductor) capacitor on float-zone silicon for RF oscillator tank, matching and bias decoupling circuits

150 pF ±2%25 V DCQ typ. 3000 @ 1 MHzTCC 0 ±30 ppm/°C0.55 × 0.55 × 0.15 mmWire bondable bare die

What This Component Is

The HACC151S25V550 is a single layer MOS capacitor: a metal top electrode, a thermally grown silicon dioxide dielectric and a semiconductor substrate that acts as the second electrode. Current flows vertically from the top pad through the oxide to the backside ground plane over a path of 0.15 mm. Because the structure has no internal electrodes, no vias and no laminated plates, it avoids the equivalent series inductance and dielectric loss that multilayer ceramic capacitors (MLCC) add at high frequency. The part is supplied as bare die in waffle pack or gel-pak and is intended for die attach plus wire bonding inside a hybrid, module or chip-on-board assembly. The double-sided ceramic margin around both electrodes gives a visible containment border for conductive adhesive and an optical reference for automated bonder alignment.

Q Factor and Its Effect on Oscillator Phase Noise

In an oscillator, the loaded Q of the resonator and the loss inside the tank set the phase noise floor. A capacitor with high Q and low ESR inside the tank keeps the resonator Q intact; a lossy capacitor lowers it and raises close-in phase noise. The measured Q of this die at 1 MHz is typically 3000, with a minimum of 2000, and the ESR at 1 GHz is typically 0.10 Ω. Both figures are measured on the reference fixture described further down, de-embedded to the die pads, at 25 °C.

The MLCC column is a comparison reference measured in the same fixture for context, not a specification of another product. Board-level phase noise depends on the resonator, the active device and the bias network as much as on the capacitor; evaluate the die inside your own tank circuit before fixing a design.

Temperature and Bias Stability

The dielectric is Class I thermal oxide, not a ferroelectric ceramic, so there is no Curie point, no domain relaxation and no voltage-dependent permittivity plateau. Practical consequences for a designer:

• Capacitance change is 0 ±30 ppm/°C, i.e. within ±0.55% over the whole −55 °C to +125 °C span (30 ppm/°C × 180 °C). Class II dielectrics such as X7R allow ±15% over the same range.
• The DC bias coefficient is below 10 ppm/V, so the capacitance at 25 V differs from the value at 0 V by less than 0.03%.
• There is no ageing slope: capacitance measured at incoming inspection is the value measured years later, whereas Class II parts drift several percent per decade hour.
• Dielectric absorption is under 0.1%, and the dielectric shows no piezoelectric response, so mechanical vibration and thermal transients do not appear as frequency modulation in a low-noise oscillator.

In a VCO or DRO tank, these properties remove the need for temperature compensation by varactor trimming and for bias derating tables in the design file. In a bias-tee or DC block, they keep the impedance at the intended value at every bias level.

Fixture description

• RF fixture: 2-port shunt-through microstrip on 0.25 mm Rogers RO4350B, 3.5 mm coaxial launchers, TRL calibration to the launcher plane, electrical de-embedding of two 1.0 mm, 25 µm Au ribbon bonds to reach the die pad reference plane.
• Capacitance and dissipation factor: Keysight E4990A with 16197A four-terminal pair fixture, open/short/load correction at every frequency point.
• Temperature: thermal chamber with the die mounted on 96% alumina via conductive epoxy; K-type thermocouple bonded within 2 mm of the die.
• Mechanical: Dage 4000 pull tester for wire pull, shear test on the die attach of first-article samples.

Assembly Instructions for HACC151S25V550

Wire bonding

• 25 µm Au thermosonic ball bonding: stage 120–150 °C, force 15–35 gf, ultrasonic 40–80 mW, time 10–20 ms; ball bond on the die pad, stitch on the substrate.
• 25 µm Al ultrasonic wedge bonding at room temperature: force 25–40 gf, ultrasonic 55–90 mW.
• Ball or wedge land at least 25 µm inside the electrode edge; the ceramic margin is the vision reference.
• Keep the wire at 1.0 mm or shorter. Every additional 0.5 mm of wire adds roughly 0.4 nH and lowers the in-circuit self-resonant frequency.
• Pull test per lot: above 6 gf for 25 µm Au wire, MIL-STD-883 Method 2011.7.

Cleaning, storage and handling

• No ultrasonic cleaning after bonding; use an IPA swab or plasma descum only.
• MSL 1, unlimited floor life at ≤30 °C / 85% RH; long-term storage in a nitrogen cabinet at 20–25 °C, 40–60% RH.
• Handle with a vacuum collet or plastic tweezers; keep metal tools away from the bond pad.

Customisation Options

Typical Applications

• Voltage controlled oscillator and dielectric resonator oscillator tank circuits in the 0.5–6 GHz range
• Impedance matching and DC blocking in RF power amplifier output networks
• Bias tee and active bias decoupling where capacitance must not shift with the bias rail
• Phase locked loop loop filters and low noise reference networks
• Optical transceiver and instrumentation front ends with long service life and no recalibration interval
• Wireless infrastructure filters, couplers and antenna tuning modules
• Industrial RF generators, test fixtures and probe card assemblies