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Ultra-High Q Factor 100 pF 30 V MOS Capacitor (HACC101S30V300) — Low ESR Miniature Single Layer RF Chip
Summary: The Hoan HACC101S30V300 is a 100 pF ±10% single-layer MOS capacitor rated at 30 V DC, delivering an ultra-high Q factor (Q>2000 @ 1 MHz, Q>300 @ 1 GHz) and ultra-low ESR (<0.08 Ω @ 1 GHz) in an ultra-miniature 0.40 × 0.40 × 0.15 mm wire-bondable bare-die package. It is engineered for low-loss RF impedance matching, DC blocking and bypass where board area and insertion loss are critical.
What Is a Single-Layer MOS Capacitor?
A MOS capacitor (Metal–Oxide–Semiconductor capacitor) is a single-layer capacitor that uses a thermally grown silicon dioxide (SiO2) dielectric on a high-resistivity silicon substrate, with metal electrodes on the top and bottom. Because there is no internal electrode stack, current flows vertically through one dielectric layer, giving a near-zero intrinsic equivalent series inductance (ESL) and a high self-resonant frequency (SRF) compared with multilayer ceramic capacitors (MLCCs).
Key Performance Advantages
- Ultra-High Q Factor — Q > 2000 at 1 MHz and Q > 300 at 1 GHz. The float-zone substrate (>1000 Ω·cm) minimises eddy-current loss, so network insertion loss is negligible and the matching inductor, not the capacitor, dominates total loss.
- Ultra-Low ESR — ESR typically below 0.08 Ω at 1 GHz, minimising I²R loss in power-amplifier bypass and DC-blocking paths.
- Miniature Chip Form Factor — the 0.40 mm bare die occupies roughly 36% of the footprint of a standard 0.50 mm chip, increasing channel density in multi-channel RF front-ends.
- Near-Zero Intrinsic Inductance — single-layer vertical current path yields intrinsic chip ESL below 0.03 nH; system resonance is set by the user-controlled bond wire.
- Stable C-V — paraelectric SiO2 shows a negligible DC-bias coefficient (<10 ppm/V) and no ferroelectric aging.
Electrical Specifications (T = 25°C unless noted)
| Parameter | Value | Condition |
| Capacitance | 100 pF ±10% (±5% available) | 1 MHz, 1.0 Vrms |
| Rated Voltage (DC) | 30 V | Continuous |
| Q Factor | >2000 @ 1 MHz / >300 @ 1 GHz | Typical |
| ESR @ 1 GHz | <0.08 Ω | Typical |
| Dissipation Factor | ≤0.15% | 1 kHz, 1.0 Vrms |
| Intrinsic Chip ESL | <0.03 nH | De-embedded |
| Self-Resonant Frequency | >8 GHz chip-level; >1.2 GHz with 0.5 mm bond wire | Typical |
| Insulation Resistance | ≥10⁴ MΩ | At rated voltage, 25°C |
| Leakage Current | <10 nA @ 25°C / <100 nA @ 125°C | At rated voltage |
| Dielectric Absorption | <0.1% | 1 kHz |
| Chip Dimensions | 0.40 × 0.40 × 0.15 mm | ±25 µm |
| Dielectric | Thermal SiO2, 300 nm | Paraelectric |
| Operating Temperature | -55°C to +125°C | Full parametric |
| Mounting | Wire Bondable / Eutectic Die Attach | AuSn or conductive epoxy |
Typical Applications
- RF power-amplifier impedance matching networks and DC blocks
- Low-loss bypass and supply decoupling above 1 GHz
- Multi-channel RF front-end and module assemblies
- Oscillator (VCO) and PLL tank circuits requiring a high-Q, low-loss element
- Test and measurement instrumentation and probe-card assemblies
