High Thermal Conductivity MOS Capacitors AuSn Backside 20V High Density Capacitor Single Layer RF Power Chip

AuSn Backside MOS Capacitor HACC101S20V101 100pF 20V High Thermal Conductivity Single Layer RF Power Chip

HACC101S20V101 Thermally-Engineered MOS Capacitor: 100pF 20V with AuSn Backside for Power RF Applications

The HACC101S20V101 is a 100pF ±10% single-layer MOS capacitor rated at 20V DC, fabricated on float-zone silicon (>1000Ω·cm) with 300nm thermal SiO₂ dielectric. Chip dimensions are 0.50mm * 0.50mm * 0.15mm with TiW-Au top metallization (2.5µm minimum Au) and TiW-Pt-Au backside (1.0µm minimum Au). An optional 80Au/20Sn eutectic pre-deposition layer (3-5µm thick) is available on the backside for customers using flux-free eutectic die attach processes.

1. Thermal Resistance Physics in Chip Capacitor Assemblies

Understanding junction-to-carrier thermal resistance (θ_JC) in a chip capacitor requires analyzing the series thermal resistances from the heat generation site to the heat sink. The total θ_JC has three principal components:

• Spreading resistance in the silicon substrate (R_spread): Heat generated in the SiO₂ dielectric and top electrode must spread through the 150µm silicon substrate to reach the backside. Silicon's thermal conductivity of 148 W/m·K at 300K gives a spreading resistance of approximately 8 K/W for a 0.50mm * 0.50mm chip. This is the dominant term in θ_JC. For comparison, an alumina substrate (24 W/m·K) would contribute roughly 60 K/W—a 7.5* penalty—explaining why thin-film capacitors on ceramic carriers have inherently higher θ_JC than silicon MOS capacitors.
• Backside metallization and interface resistance (R_interface): The 1.0µm gold backside layer has negligible bulk thermal resistance (~0.001 K/W). The thermal boundary resistance at the Au-to-AuSn interface, when properly prepared, is below 10^-8 m²·K/W, contributing under 0.04 K/W for the 0.25mm² chip area.
• Die-attach bond line resistance (R_attach): This is the most variable term and depends strongly on material choice. For a 5µm-thick bond line: AuSn eutectic (57 W/m·K) yields ~0.35 K/W; silver conductive epoxy (5 W/m·K typical) yields ~4 K/W; standard PbSn solder (50 W/m·K) yields ~0.4 K/W but is not RoHS-compliant. The AuSn pre-deposition option ensures a controlled, thin, void-free bond line that minimizes this term.

The measured total θ_JC for a 0.50mm chip with AuSn attach to a CuMo carrier is under 30 K/W, consistent with the sum of these three contributions plus a small margin for measurement uncertainty and bond line voiding.

2. RF Power Derating Methodology and Reliability

RF power handling capability is not a single number—it depends on frequency, duty cycle, ambient temperature, and acceptable lifetime. The HACC101S20V101 is characterized to support informed derating:

• Voltage derating: The 20V DC continuous rating provides a 5:1 margin to the >100V dielectric breakdown strength. For RF applications, the peak voltage (V_peak = V_{DC_bias} + V_{RF_amplitude}) should not exceed the 20V rating. In a 50Ω system without DC bias, this corresponds to 4W of CW RF power (V_peak = √(2PR) = √(2*4*50) = 20V). For modulated signals with a peak-to-average ratio of 8-10dB (typical for 5G OFDM), the average power at the same peak voltage limit can be 6-10* lower, or approximately 0.4-0.7W average.
• Current derating: The ESR at 1GHz is typically under 0.1Ω. At 0.5A RMS (12.5W in 50Ω), I²R heating is 25mW. With θ_JC < 30 K/W, this produces a junction temperature rise of under 0.75°C above the carrier—negligible for most applications. Continuous current to 1.0A RMS (50mW dissipation, ~1.5°C rise) is well within the safe operating area.
• Temperature derating: The maximum junction temperature is 125°C. At a carrier temperature of 85°C (typical for base station power amplifier pallets), the allowed temperature rise is 40°C, corresponding to a maximum power dissipation of 1.3W (θ_JC * ΔT = 30 * 40 = 1.2W, with conservative rounding). This is far above the typical dissipation in any practical bypass or DC-block application.
• Power cycling reliability: Repeated thermal cycling from power dissipation can induce fatigue in the die-attach bond line. AuSn eutectic joints tested under 100,000 power cycles (ΔT_J = 40°C, 30-second period) showed less than 10% increase in θ_JC, indicating minimal bond line degradation. The ductile AuSn alloy accommodates the cyclic strain through creep relaxation without void coalescence or delamination.

3. AuSn Eutectic Metallurgy and Process Integration

The 80Au/20Sn eutectic system (melting point 280°C) is widely used in high-reliability hybrid assembly. Understanding its metallurgy helps optimize the assembly process:

• Phase composition: The eutectic microstructure consists of a fine lamellar mixture of the Au₅Sn (ζ-phase) and AuSn (δ-phase) intermetallic compounds. Both phases are thermodynamically stable and do not undergo significant microstructural coarsening during extended high-temperature operation. The Au₅Sn phase provides mechanical strength, while the AuSn phase contributes ductility.
• Pre-deposition quality control: The 3-5µm AuSn layer on the chip backside is deposited by thermal evaporation with thickness uniformity of ±10% across a wafer. Composition is verified by X-ray fluorescence (XRF) on witness samples from each deposition run. The Au:Sn weight ratio is controlled to 80:20 ±2% to ensure eutectic melting behavior without a wide pasty range.
• Reflow process window: Peak reflow temperature should be 300-320°C (20-40°C above the 280°C eutectic point). The time above liquidus should be 30-60 seconds. Forming gas (95% N₂ / 5% H₂) atmosphere prevents tin oxidation. No flux is required—the hydrogen in the forming gas reduces any native tin oxide on the pre-deposited surface. Oxygen concentration in the reflow chamber should be maintained below 10ppm.
• Intermetallic formation at the gold interface: During reflow, the liquid AuSn eutectic dissolves a small amount of gold from both the chip backside and the substrate pad, shifting the composition slightly toward the gold-rich side of the eutectic. This results in a thin layer of primary Au₅Sn at both interfaces after solidification, which actually strengthens the bond. Excess gold dissolution (>5µm from each surface) can raise the liquidus temperature, so total gold thickness on both mating surfaces is accounted for in process design.

Key Features

• Superior Thermal Conductivity: 148 W/m·K silicon substrate minimizes spreading resistance (8 K/W). AuSn bond line at 57 W/m·K provides 10* lower thermal resistance than conductive epoxy. Total θ_JC under 30 K/W. 100k power cycles with under 10% θ_JC degradation.
• High RF Power Handling: 20V DC rating with >100V breakdown (5:1 margin). ESR <0.1Ω@1GHz limits I²R heating below 50mW at 1A RMS. 125°C maximum junction temperature allows 1.2W dissipation at 85°C carrier with AuSn attach.
• AuSn Pre-Deposition Backside: 3-5µm 80Au/20Sn eutectic layer, ±10% thickness uniformity, XRF composition verified. Flux-free reflow at 300-320°C in N₂/H₂. Die shear >2.5kgf. Under 5% void area by X-ray inspection.
• SiO₂ Dielectric Stability: Near-zero dielectric heating (tan δ <0.001@1GHz). No thermal runaway risk—leakage doubles per 30-40°C vs. exponential runaway in some ferroelectric dielectrics.
• Near-Zero ESL: Intrinsic chip ESL under 0.05nH, SRF >8GHz for 100pF value.

Electrical Specifications (T = 25°C unless noted)

Thermal Design Guide

Carrier material selection: The carrier material beneath the chip significantly affects total thermal resistance from junction to ambient. CuMo (7-9 ppm/°C CTE, 160-180 W/m·K) provides the best combination of CTE match to silicon and thermal conductivity. AlN ceramic (4.5 ppm/°C CTE, 170 W/m·K) is an alternative for alumina-compatible processes. Copper-tungsten (CuW, 6-9 ppm/°C CTE, 180-200 W/m·K) offers slightly higher conductivity at increased weight and cost.

Multiple chip thermal coupling: In multi-chip modules, adjacent power devices (GaN HEMTs, LDMOS transistors) can raise the local carrier temperature well above the system ambient. When placing bypass capacitors near power transistors, account for the lateral temperature gradient across the carrier. A conservative guideline is to maintain at least one chip-width (0.50mm) of clearance between the capacitor and the power device backside to avoid excessive conductive heating through the carrier.

Bond wire current capacity: A single 25µm diameter gold bond wire has a fusing current of approximately 0.8A DC. For RF currents above 0.5A RMS, use two parallel bond wires, which also halves the inductance contribution. At 1GHz, the skin depth in gold is approximately 2µm—the entire 25µm wire cross-section carries current, so skin effect does not significantly degrade the current-carrying capacity.

Typical Applications

• GaN-on-SiC power amplifier output matching networks where baseplate temperatures reach 85°C and capacitor dissipation must be conducted away with minimum temperature rise
• High-power RF switch bias networks in time-division duplex (TDD) systems with high per-branch duty cycles
• Microwave point-to-point radio transmitters operating at 1-10W CW output power
• Industrial RF plasma generators (13.56MHz, 27.12MHz ISM bands) with multi-hundred-watt output stages
• Phased-array T/R module power supply decoupling with constrained thermal paths
• Wireless infrastructure remote radio units (RRU) with passive convection cooling in outdoor enclosures

Assembly Process Notes

Standard backside: Apply AuSn solder preform or paste, reflow at 300-320°C peak in N₂/H₂ forming gas. Alternatively, silver-filled conductive epoxy (cure per manufacturer profile, typically 150°C for 1 hour). AuSn pre-deposited backside: Place chip directly onto Au-plated pad, reflow without additional solder or flux. Wire bonding: 25µm Au thermosonic ball bonding at 120-150°C stage, 25-35gf force, >6gf pull strength. For RF currents >0.5A RMS, use two parallel 25µm bond wires. Inspection: X-ray for die-attach void verification, optical for bond wire placement and heel integrity.

Contact us for θ_JC measurement data, power cycling reliability reports, or AuSn process integration support.