Low Quantum Capacitance MOS Capacitor 100pF 200V Ultra-High Dielectric Breakdown Field Single Layer Chip For HV RF

HACC101S200V801 Low Quantum Capacitance MOS Capacitor 100pF 200V Single Layer Wire Bondable RF Chip

Product definition: The HACC101S200V801 is a single-layer metal-oxide-semiconductor (MOS) capacitor built on a high-resistivity float-zone silicon substrate with a dense, thermally grown silicon dioxide (SiO₂) dielectric. It delivers 100 pF (±10%) at a 200 V DC working voltage in a 0.50 mm × 0.50 mm × 0.15 mm wire-bondable chip. The same device family is also described as a single layer capacitor (SLC) chip, an RF chip capacitor, a wire bondable capacitor, or a MOS chip capacitor.

Its two defining characteristics are a low quantum capacitance effect and an ultra-high dielectric breakdown field (>10 MV/cm). Together they support a flat, ultra-linear C-V response and a high 200 V rating in a compact die.

Key Features

Low Quantum Capacitance Effect

In any MOS structure the measured capacitance is a series combination of the oxide capacitance (Cox) and the semiconductor capacitance, which includes the quantum capacitance (Cq) associated with the finite density of states at the silicon surface. When Cq is comparable to Cox the total capacitance becomes bias- and frequency-dependent and drops below the expected oxide value. The HACC101S200V801 is designed with a heavily doped float-zone silicon electrode and an optimized interface so that Cq stays more than 10× larger than Cox. The quantum capacitance effect is therefore negligible and the device behaves as a nearly ideal oxide capacitor: the measured value equals the geometric oxide capacitance, flat across the full bias range and stable with frequency.

Ultra-High Dielectric Breakdown Field (>10 MV/cm)

The dielectric is a high-quality thermal SiO₂ with low defect density and an intrinsic breakdown field exceeding 10 MV/cm. This dielectric robustness supports a continuous 200 V DC rating and a dielectric withstanding voltage above 500 V DC (250% of rated) in a compact 20 mil wire-bondable chip, providing generous headroom for high-voltage RF signal chains, bias injection, and transient events. The dielectric withstanding voltage is verified on 100% of production units.

Stable Low-Loss Performance

Temperature coefficient of capacitance is approximately +35 ppm/°C, nearly linear from -55°C to +125°C, with a low DC bias coefficient (<10 ppm/V). Q exceeds 2000 at 1 MHz, ESL is below 0.05 nH, and leakage current stays below 10 nA at 200 V, making the device suitable for precision RF bypass, DC blocking, and matching networks.

Electrical Specifications (T = 25°C unless noted)

Reliability and Qualification (typical values)

Typical Applications

• High-voltage RF DC blocking and bias injection networks
• Impedance matching in power amplifiers and antenna front-ends operating above 100 V
• Precision bypass and decoupling where flat C-V and low frequency dependence are critical
• Test and measurement instrumentation and VNA calibration standards
• Medical RF subsystems and industrial RF generation equipment