CTE Matched MOS Capacitors Ultra High SRF 15V Single Layer Capacitor Chip For Hybrid Microcircuits

CTE Matched MOS Capacitor HACC101S15V500 100pF 15V Ultra-High SRF Single Layer Chip for Hybrid Microcircuits

HACC101S15V500 CTE-Matched MOS Capacitor: 100pF 15V with Ultra-High Self-Resonance and Dual Backside Options

The HACC101S15V500 is a 100pF ±10% single-layer MOS capacitor rated at 15V DC, fabricated on float-zone silicon (>1000Ω·cm) with 300nm thermal SiO₂ dielectric. Chip dimensions are 0.50mm * 0.50mm * 0.15mm with TiW-Au top metallization (2.5µm minimum Au). The backside is available in two configurations: standard TiW-Pt-Au for both eutectic solder and conductive epoxy die attach, or an optional Au-only finish optimized for silver-filled epoxy wetting.

1. Coefficient of Thermal Expansion Matching in Hybrid Assemblies

Thermomechanical stress is a leading cause of capacitor failure in hybrid microcircuits subjected to temperature cycling. The mismatch in coefficient of thermal expansion (CTE) between the capacitor chip and the carrier substrate generates shear stress in the die-attach bond line during every temperature excursion. The HACC101S15V500 minimizes this stress through material selection:

• Silicon CTE (2.6 ppm/°C): Single-crystal silicon has a CTE of 2.6 ppm/°C at 300K, making it an excellent CTE match to common carrier materials used in RF and microwave hybrids. Alumina (Al₂O₃, 6.7 ppm/°C) produces a CTE mismatch of 4.1 ppm/°C—roughly half the mismatch of a typical barium titanate ceramic capacitor (CTE ~10 ppm/°C) on the same carrier. Aluminum nitride (AlN, 4.5 ppm/°C) is even better matched at 1.9 ppm/°C difference. For the lowest stress, copper-molybdenum (CuMo, 7-9 ppm/°C) and copper-tungsten (CuW, 6-9 ppm/°C) composites can be formulated to approach silicon's CTE while maintaining high thermal conductivity.
• Stress accommodation in the bond line: Even with close CTE matching, a finite shear stress develops across the die-attach interface during temperature cycling. The stress magnitude is proportional to Δα * ΔT * E_attach * (chip length / bond line thickness), where Δα is the CTE mismatch, ΔT is the temperature range, and E_attach is the elastic modulus of the die-attach material. AuSn eutectic (E ≈ 70 GPa) is relatively stiff and benefits most from the close CTE match. Conductive epoxy (E ≈ 5-10 GPa) is more compliant and can tolerate larger CTE mismatches without delamination, but at the cost of higher thermal resistance.
• Temperature cycling qualification: Assembled chips on alumina carriers with AuSn attach have been tested through 500 cycles of -65°C to +150°C (ΔT = 215°C) with no delamination observed by scanning acoustic microscopy (SAM) and under 2% capacitance shift. This performance is enabled by the inherently low CTE mismatch of the silicon-on-ceramic materials system.

2. Ultra-High Self-Resonant Frequency Through Minimal Parasitic Inductance

The self-resonant frequency (SRF) of a capacitor—the frequency at which the parasitic series inductance resonates with the capacitance, above which the component behaves inductively—determines the maximum usable frequency for bypass and coupling applications. The HACC101S15V500 achieves an ultra-high SRF through its single-layer architecture:

• SRF calculation: For the 100pF value with intrinsic chip ESL under 0.05nH, the chip-level self-resonance occurs at f_SRF = 1/(2π√(LC)) ≈ 1/(2π√(0.05*10⁻⁹ * 100*10⁻¹²)) ≈ 2.25GHz for the chip alone. However, in a practical assembly, the bond wire inductance (approximately 0.35nH for a 0.5mm-long 25µm Au wire) dominates. The system SRF is then approximately 1/(2π√(0.4*10⁻⁹ * 100*10⁻¹²)) ≈ 800MHz—still well within the usable range for many RF applications.
• Pushing SRF higher: For applications requiring SRF above 2GHz, multiple parallel bond wires reduce the effective inductance proportionally. Two parallel bond wires halve the inductance to ~0.2nH, shifting the SRF to approximately 1.1GHz. Three wires reduce it further to ~0.13nH, with SRF near 1.4GHz. Ribbon bonding (e.g., 25µm * 75µm gold ribbon) provides an alternative low-inductance connection with approximately 0.2nH/mm—roughly half the inductance of an equivalent cross-section round wire.
• Comparison with MLCC: A typical 100pF MLCC in 0402 package has an ESL of approximately 0.4-0.6nH—an order of magnitude higher than the intrinsic chip ESL of the HACC101S15V500. The MLCC's SRF is therefore limited to approximately 600-800MHz even before considering the additional inductance of PCB traces and vias. For applications above 1GHz, the single-layer MOS capacitor provides a clear advantage in usable bandwidth.

3. Backside Metallization Options Optimized for Different Die-Attach Methods

The backside metallization directly influences die-attach quality, thermal resistance, and long-term reliability. The HACC101S15V500 offers two backside configurations to match the customer's assembly process:

• Standard TiW-Pt-Au backside: A 100nm TiW adhesion/barrier layer, followed by a 100nm platinum (Pt) barrier, with a 1.0µm minimum gold outer layer. The Pt barrier is critical for silver-filled epoxy applications: without it, silver ions from the epoxy can diffuse into the gold layer and form Au-Ag intermetallic compounds at elevated temperatures, which are brittle and can reduce die shear strength over time. The Pt layer is chemically inert to both gold and silver, acting as an effective diffusion barrier. For eutectic solder attach, the gold outer layer dissolves into the AuSn solder during reflow, exposing the Pt barrier which remains intact and prevents solder from reaching the TiW adhesion layer.
• Au-only backside (optional): For customers using exclusively AuSn eutectic solder attach, an Au-only backside (no Pt or TiW, gold thickness 2.5µm minimum) is available. The thicker gold layer provides additional solderable volume for the AuSn reflow process, ensuring complete wetting even if some gold is consumed by dissolution into the molten solder. This option is not recommended for epoxy attach due to the absence of the Pt diffusion barrier.
• Surface preparation and wetting: Gold surfaces are susceptible to organic contamination from air exposure, which can degrade solder wetting. Chips are packaged immediately after backside deposition in vacuum-sealed moisture barrier bags. For best results, die attach should be performed within 72 hours of opening the sealed package. If extended exposure occurs, a brief oxygen plasma clean (50W, 30 seconds) restores the gold surface to a wettable condition without damaging the metallization.

Key Features

• Perfect CTE Matching: Silicon CTE of 2.6 ppm/°C closely matches alumina (6.7), AlN (4.5), CuMo (7-9), and CuW (6-9) carriers. 500 temperature cycles (-65°C to +150°C) with under 2% capacitance shift and no SAM-detectable delamination.
• Ultra-High SRF: Intrinsic chip ESL under 0.05nH yields chip-level SRF above 2.2GHz for 100pF. Parallel bond wires or ribbon bonding push system SRF above 1GHz. 10* lower ESL than equivalent-capacitance MLCC in 0402 package.
• Dual Backside Metallization Options: TiW-Pt-Au for universal epoxy and solder compatibility with Pt diffusion barrier. Au-only option for dedicated AuSn eutectic attach lines with enhanced solderable volume.
• SiO₂ Dielectric: Thermal oxide with zero DC bias capacitance droop, tan δ under 0.001 at 1GHz, and +35ppm/°C TCC.
• Wafer-Level Tested: 100% DC probe for capacitance, leakage at rated voltage, and breakdown voltage before dicing.

Electrical Specifications (T = 25°C unless noted)

CTE Compatibility Guide

Typical Applications

• Hybrid microcircuits on alumina or AlN substrates requiring close CTE matching for high-reliability temperature cycling
• Broadband microwave bypass above 1GHz where MLCC self-resonance limits usable bandwidth
• Hermetic packaged RF modules (HTCC/LTCC base) where capacitor-to-package CTE matching prevents lid-seal stress
• Phased-array T/R modules on CuMo carriers subjected to wide ambient temperature swings in outdoor installations
• Cryogenic RF systems (e.g., quantum computing readout chains operating at 4K) where differential contraction between components must be managed

Assembly Guidelines

Die attach: TiW-Pt-Au backside compatible with AuSn eutectic (300-320°C, N₂/H₂) and Ag conductive epoxy (150°C cure). Au-only backside for AuSn eutectic only. Wire bonding: 25µm Au ball bonding or Al wedge bonding. For SRF optimization above 1GHz, use two parallel 25µm bond wires or 25µm * 75µm Au ribbon. Plasma clean: If chips have been exposed to ambient air beyond 72 hours, apply 50W O₂ plasma for 30 seconds before die attach to restore surface wettability.

Contact us for CTE compatibility analysis for your specific carrier material, SRF optimization support, or backside metallization selection guidance.