products details

Created with Pixso. Home Created with Pixso. Products Created with Pixso.
MOS Capacitors
Created with Pixso.

Zero-TCESR MOS Capacitor 100pF 50V Single Layer Chip For Ultra-Stable RF Gain

Zero-TCESR MOS Capacitor 100pF 50V Single Layer Chip For Ultra-Stable RF Gain

Brand Name: Hoan
Model Number: HACC101S50V200
MOQ: 10 Pieces
Payment Terms: T/T,L/C,D/A,D/P
Detail Information
Place of Origin:
Shaanxi, China
Certification:
ISO 9001:2015, RoHS
Chip Dimensions:
0.50 X 0.50 X 0.15mm
Top Metallization:
TiW + Au, 2.5µm Min
Mounting Type:
Wire Bondable / Eutectic Die Attach
Operating Temperature:
-55°C To +125°C
RoHS:
Compliant (EU 2015/863)
Customization:
Capacitance 10pF-1000pF, Geometry Up To 4:1, Bordered Electrode, Floating Backside
Highlight:

Zero-TCESR MOS Capacitor 100pF

,

50V Single Layer Chip Capacitor

,

Ultra-Stable RF Gain MOS Capacitor

Product Description

HACC101S50V200 Zero-TCESR MOS Capacitor — 100pF 50V Single Layer RF Chip


Product overview: The HACC101S50V200 is a single-layer metal-oxide-semiconductor (MOS) capacitor with a nominal capacitance of 100pF ±10% and a 50V DC working voltage. It is built on a float-zone silicon substrate with a 300nm thermal silicon dioxide (SiO2) dielectric and a TiW-Au metallization stack. Its defining property is a Zero-TCESR design — the temperature coefficient of equivalent series resistance is close to zero, so ESR stays nearly constant from -55°C to +125°C. This suits RF signal chains that require stable gain over temperature.



What Is Zero-TCESR?


TCESR stands for Temperature Coefficient of Equivalent Series Resistance. A Zero-TCESR capacitor is one whose ESR changes very little with temperature. In an RF amplifier or matching network, ESR adds a small resistive loss in series with the signal path. If that loss grows as the board heats up, the gain of the stage falls. A capacitor with near-zero TCESR keeps that loss essentially constant, so gain stability is maintained across the operating temperature range without additional compensation networks.


Key Specifications (T = 25°C unless noted)


Parameter Value Condition
Capacitance 100pF ±10% 1MHz, 1.0Vrms
Rated DC voltage 50V Continuous
Dielectric strength >125V DC 1 minute, 25°C
Temperature coefficient of ESR Zero-TCESR, <±5% variation -55°C to +125°C
ESR at 1GHz <0.08 Ω Typical
Q factor at 1MHz >2000 Typical
Q factor at 1GHz >300 Typical
Intrinsic chip ESL <0.05nH De-embedded from S-parameters
TCC +35ppm/°C -55°C to +125°C
Leakage current <10nA 50V DC, 25°C
Dielectric Thermal SiO2, 300nm
Substrate Float-zone Si, >1000 Ω·cm
Chip dimensions 0.50 × 0.50 × 0.15mm ±0.025mm
Top metallization TiW + Au, 2.5µm min Wire bondable
Backside metallization TiW-Pt-Au, Au 1.0µm min Die attach
Operating temperature -55°C to +125°C
RoHS Compliant EU 2015/863


Typical Applications


  • Low-noise amplifier (LNA) matching and gain stages
  • RF and microwave amplifier bias decoupling
  • Phased-array and beamformer RF channels
  • Telecom radio front-ends
  • Test and measurement instrumentation front-ends
  • Filter, coupler, and matching networks


Zero-TCESR MOS Capacitor 100pF 50V Single Layer Chip For Ultra-Stable RF Gain