| Brand Name: | Hoan |
| Model Number: | HACC101S50V200 |
| MOQ: | 10 Pieces |
| Payment Terms: | T/T,L/C,D/A,D/P |
Product overview: The HACC101S50V200 is a single-layer metal-oxide-semiconductor (MOS) capacitor with a nominal capacitance of 100pF ±10% and a 50V DC working voltage. It is built on a float-zone silicon substrate with a 300nm thermal silicon dioxide (SiO2) dielectric and a TiW-Au metallization stack. Its defining property is a Zero-TCESR design — the temperature coefficient of equivalent series resistance is close to zero, so ESR stays nearly constant from -55°C to +125°C. This suits RF signal chains that require stable gain over temperature.
TCESR stands for Temperature Coefficient of Equivalent Series Resistance. A Zero-TCESR capacitor is one whose ESR changes very little with temperature. In an RF amplifier or matching network, ESR adds a small resistive loss in series with the signal path. If that loss grows as the board heats up, the gain of the stage falls. A capacitor with near-zero TCESR keeps that loss essentially constant, so gain stability is maintained across the operating temperature range without additional compensation networks.
| Parameter | Value | Condition |
| Capacitance | 100pF ±10% | 1MHz, 1.0Vrms |
| Rated DC voltage | 50V | Continuous |
| Dielectric strength | >125V DC | 1 minute, 25°C |
| Temperature coefficient of ESR | Zero-TCESR, <±5% variation | -55°C to +125°C |
| ESR at 1GHz | <0.08 Ω | Typical |
| Q factor at 1MHz | >2000 | Typical |
| Q factor at 1GHz | >300 | Typical |
| Intrinsic chip ESL | <0.05nH | De-embedded from S-parameters |
| TCC | +35ppm/°C | -55°C to +125°C |
| Leakage current | <10nA | 50V DC, 25°C |
| Dielectric | Thermal SiO2, 300nm | — |
| Substrate | Float-zone Si, >1000 Ω·cm | — |
| Chip dimensions | 0.50 × 0.50 × 0.15mm | ±0.025mm |
| Top metallization | TiW + Au, 2.5µm min | Wire bondable |
| Backside metallization | TiW-Pt-Au, Au 1.0µm min | Die attach |
| Operating temperature | -55°C to +125°C | — |
| RoHS | Compliant | EU 2015/863 |
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