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Oxygen-Free Ohmic Contact MOS Capacitor 470pF 100V Low ESR Single Layer Chip For Energy Harvesting Discharge

Oxygen-Free Ohmic Contact MOS Capacitor 470pF 100V Low ESR Single Layer Chip For Energy Harvesting Discharge

Brand Name: Hoan
Model Number: HACC471S100V701
MOQ: 10 Pieces
Payment Terms: L/C,D/A,D/P,T/T
Detail Information
Place of Origin:
Shaanxi, China
Certification:
ISO 9001:2015, RoHS
ESD Tolerance:
>2 KV HBM, Class 2 (JESD22-A114)
Operating / Storage Temperature:
-55°C To +200°C / -65°C To +150°C
Chip Dimensions:
0.65 × 0.65 × 0.20 Mm (±25 µm); Custom Geometry Up To 4:1 Aspect Ratio
Metallization:
TiW-Au Top (≥2.5 µm Au) / Oxygen-free Pure-Au Ohmic Backside (AuSn / Solder / Silver Epoxy)
Mounting Type:
Wire Bondable / AuSn Eutectic / Solder / Conductive Epoxy
Testing:
100% Production Tested (C, DF, Leakage, DWV); KGD Wafer Map Per Lot
Highlight:

oxygen-free MOS capacitor 470pF

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low ESR MOS capacitor 100V

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single layer chip capacitor energy harvesting

Product Description

HACC471S100V701 MOS Capacitor — 470 pF 100 V with Oxygen-Free Ohmic Contact and Low-ESR Energy Discharge


The HACC471S100V701 is a 470 pF ±10% single-layer MOS capacitor rated at 100 V DC, fabricated on a conductive silicon substrate with an oxygen-free pure-gold ohmic backside contact. By eliminating interfacial oxide at the backside metal-to-silicon junction, the device achieves low interfacial and series resistance, which directly improves discharge efficiency in energy-harvesting storage and pulsed-power applications. A MOS capacitor is a single-layer capacitor formed by a metal-oxide-semiconductor structure (thermal silicon dioxide on a conductive silicon substrate), storing energy as ½CV². Low ESR and high Q ensure that stored charge is delivered to the load with minimal loss.


Oxygen-Free Ohmic Contacts for Low Interfacial Resistance


  • Oxygen-free process: the backside ohmic contact is formed on low-resistivity silicon without exposure to oxygen, avoiding a high-resistance interfacial oxide layer between metal and substrate;
  • Low interfacial resistance: the pure-Au ohmic contact minimizes contact resistance, keeping total ESR below 0.1 Ω at 1 GHz and series resistance low for discharge currents;
  • Conductive silicon substrate: substrate resistivity is selectable per application (custom option), from high-resistivity for RF bias decoupling to low-resistivity for low-loss charge delivery;
  • Assembly flexible: the Au backside supports AuSn eutectic, SAC solder and conductive epoxy attach; an Au-only finish is available for silver-filled epoxy.


Electrical Characteristics (typical, 25°C unless noted)

Nominal Capacitance 470 pF ±10% (1 kHz, 1.0 Vrms); tighter tolerance and matched sets available
Rated Voltage 100 V DC
Dielectric Withstanding Voltage 250 V DC (250% rated, 5 s, 100% tested)
Temperature Coefficient (TCC) +35 ppm/°C over -55°C to +200°C
Dissipation Factor ≤0.15% at 1 kHz, 1.0 Vrms
Q Factor >2000 at 1 MHz
ESR <0.1 Ω @ 1 GHz (low interfacial resistance design)
Intrinsic Chip ESL <0.05 nH (de-embedded)
Chip-Level SRF >1 GHz (470 pF)
Leakage Current <10 nA at 25°C; <500 nA at 200°C (at rated voltage)
Insulation Resistance ≥104 MΩ at rated voltage, 25°C
ESD Tolerance >2 kV HBM, Class 2 per JESD22-A114
Operating / Storage Temperature -55°C to +200°C / -65°C to +150°C
Standard Die Size 0.65 × 0.65 × 0.20 mm (±25 µm); custom geometry, aspect ratio up to 4:1
Metallization TiW-Au top (≥2.5 µm Au, wire bondable); oxygen-free pure-Au ohmic backside


Typical Applications


Energy-harvesting storage and pulsed discharge in piezo, photovoltaic and thermoelectric systems; snubber and clamp networks of power converters; gate-drive decoupling in GaN and SiC modules; RF power amplifier bias networks; wireless sensor nodes and self-powered IoT modules requiring low-leakage, high-efficiency charge delivery.


Oxygen-Free Ohmic Contact MOS Capacitor 470pF 100V Low ESR Single Layer Chip For Energy Harvesting Discharge