| Brand Name: | Hoan |
| Model Number: | HACC102T50V601 |
| MOQ: | 10 Pieces |
| Payment Terms: | L/C,D/A,D/P,T/T |
The HACC102T50V601 is a 1000 pF ±10% single-layer MOS capacitor rated at 50 V DC, built on a 3D deep-trench silicon architecture in which deep trenches etched into the silicon substrate multiply the effective electrode area within the same die footprint. The capacitor delivers 1000 pF in a 0.50 mm × 0.50 mm die; for reference, planar 1000 pF MOS capacitors in this series use 0.75 mm-class die, so the trench design provides roughly twice the capacitance per unit area for space-constrained hybrid modules. A MOS capacitor is a single-layer capacitor formed by a metal-oxide-semiconductor structure (thermal silicon dioxide on a conductive silicon substrate), valued for low ESL, stable capacitance and high insulation resistance.
| Nominal Capacitance | 1000 pF ±10% (1 kHz, 1.0 Vrms); ±5% available |
| Rated Voltage | 50 V DC |
| Dielectric Withstanding Voltage | 125 V DC (250% rated, 5 s, 100% tested) |
| Temperature Coefficient (TCC) | +35 ppm/°C over -55°C to +200°C |
| Dissipation Factor | ≤0.15% at 1 kHz, 1.0 Vrms |
| Q Factor | >2000 at 1 MHz |
| ESR | <0.1 Ω @ 1 GHz |
| Intrinsic Chip ESL | <0.05 nH (de-embedded) |
| Leakage Current | <10 nA at 25°C; <500 nA at 200°C (at rated voltage) |
| Insulation Resistance | ≥104 MΩ at rated voltage, 25°C |
| ESD Tolerance | >2 kV HBM, Class 2 per JESD22-A114 |
| Operating / Storage Temperature | -55°C to +200°C / -65°C to +150°C |
| Standard Die Size | 0.50 × 0.50 × 0.18 mm (±25 µm); custom geometry, aspect ratio up to 4:1 |
| Metallization | TiW-Au top (≥2.5 µm Au, wire bondable); TiW-Pt-Au backside for AuSn / conductive epoxy |
Compact DC bias decoupling and bypass in hybrid microcircuits and multi-chip modules; RF power amplifier bias networks; space-constrained microwave assemblies; filter and timing networks requiring bias-stable capacitance; high-density energy storage in pulsed circuits.
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