Advanced Dielectric Passivation MOS Capacitors Step Edge Geometry 1000 pF 100V Single Layer Chip For Arc Over Prevention

HACC102S100V301 1000pF 100V MOS Capacitor Advanced Dielectric Passivation Step Edge Geometry Moisture Resistant Single Layer Chip

The HACC102S100V301 is a 1000pF ±10% single-layer MOS capacitor rated at 100V DC, fabricated on float-zone silicon (>1000 Ω·cm) with an amorphous thermal SiO₂ dielectric and TiW-Au / TiW-Pt-Au metallization. Standard chip dimensions are 0.75mm × 0.75mm × 0.20mm (±25µm), with custom capacitance, voltage rating, die geometry (aspect ratio up to 4:1), and backside metallization available on request. It is engineered for hybrid microcircuits where humidity exposure, high DC bias, and reduced-pressure operation demand more from a chip capacitor than standard devices can deliver.

Advanced Dielectric Passivation for Moisture Resistance

The exposed thermal SiO₂ surface of a bare MOS capacitor is hydrophilic and can adsorb moisture and ionic contamination during assembly, which creates a surface leakage path and shifts the effective capacitance of the device. The HACC102S100V301 applies an advanced dielectric passivation layer over the full dielectric surface to suppress moisture adsorption and keep the device electrically stable:

• Moisture sensitivity MSL 1: Rated unlimited floor life per J-STD-020. The passivated surface removes the need for dry-bake before die attach or wire bonding in hybrid assembly lines.
• Surface leakage suppression: The passivation blocks water film formation and ionic contamination (flux residue, handling residue) on the dielectric, maintaining stable insulation resistance in humid production environments.
• Stable leakage current: Leakage current is <10nA at 25°C and <500nA at 200°C at 100V DC, with insulation resistance ≥10⁴ MΩ at rated voltage, 25°C.
• Thermal cycling robustness: The passivation layer and TiW adhesion base are matched to the silicon substrate, remaining intact through repeated -55°C to +200°C thermal cycles without cracking or delamination.

Electrical Characteristics and Reliability

• Capacitance: 1000pF ±10% (±5% available on custom orders)
• Temperature coefficient (TCC): +35 ppm/°C over -55°C to +200°C
• Q factor: >2000 at 1MHz, >200 at 1GHz
• Dissipation factor: ≤0.15% at 1kHz, 1.0Vrms
• ESR at 1GHz: <0.1Ω
• Intrinsic chip ESL: <0.05nH (de-embedded); chip-level SRF >1.5GHz; system SRF >600MHz with 0.5mm Au bond wire
• ESD tolerance: >2kV HBM (Class 2 per JESD22-A114)
• Wire bond pull strength: >6gf for 25µm Au wire (MIL-STD-883 Method 2011.7)
• Operating temperature: -55°C to +200°C; storage: -65°C to +150°C
• Reliability: 100% production tested (capacitance, DF, leakage, DWV), KGD wafer map per lot, SPC-controlled per wafer lot

Typical Applications

High-voltage DC bias networks and decoupling in RF power amplifiers, DC blocking in microwave modules, satellite and space payload electronics, defense hybrid microcircuits, high-altitude avionics, and harsh-environment industrial controls where moisture, temperature extremes, and high bias voltage are present.