Zero Dielectric Memory 1000pF 80V MOS Capacitor Ultra-Linear CV Characteristics Paraelectric SiO2 Single Layer RF Chip

HACC102S80V500 Zero Dielectric Memory MOS Capacitor: 1000pF 80V with Ultra-Linear C-V Characteristics and Paraelectric SiO₂ Dielectric

The HACC102S80V500 is a 1000pF ±10% single-layer MOS capacitor rated at 80V DC, fabricated on float-zone silicon (>1000Ω·cm) with 300nm thermally-grown paraelectric SiO₂ dielectric. Chip dimensions are 0.75mm × 0.75mm × 0.15mm with TiW-Au top metallization (2.5µm minimum Au) and TiW-Pt-Au backside (1.0µm minimum Au, Pt barrier). This device is engineered for precision analog and RF applications where dielectric memory effects, capacitance nonlinearity with voltage, and long-term capacitance drift are design-limiting factors. Fully customizable: capacitance from 10pF to 1000pF, voltage ratings from 6.3V to 100V, custom chip geometries, and alternative metallization options available.

1. Zero Dielectric Memory—The Paraelectric Advantage of Thermal SiO₂

Dielectric memory is a fundamental limitation of ferroelectric ceramic dielectrics used in Class II MLCCs (X7R, X5R, Y5V) and many thin-film capacitors. In ferroelectric materials like barium titanate (BaTiO₃), the spontaneous polarization of crystalline domains creates a voltage-dependent capacitance that exhibits both hysteresis (memory of prior bias state) and logarithmic aging (relaxation of domain polarization over time). The HACC102S80V500 eliminates both effects entirely by using thermally-grown silicon dioxide—a purely paraelectric dielectric with no ferroelectric domains:

• Zero Dielectric Absorption: When a capacitor is momentarily shorted after being charged, an ideal dielectric returns to zero voltage. In practice, ferroelectric dielectrics retain a residual voltage (typically 0.1–5% of the original charge) that slowly decays over seconds to minutes—a phenomenon known as dielectric absorption or soakage. The HACC102S80V500's paraelectric SiO₂ exhibits dielectric absorption below 0.1% at 1kHz—an order of magnitude improvement over Class II ceramics (2–5%). In precision sample-and-hold circuits, a 5% dielectric absorption error translates directly to a 5% voltage measurement error. The <0.1% absorption of SiO₂ reduces this error to negligible levels.
• Zero Aging Rate: Class II X7R capacitors exhibit a logarithmic capacitance decay of approximately 3–5% per decade-hour due to ferroelectric domain relaxation. A 1000pF X7R capacitor measured at t=0 will decay to approximately 950pF after 1000 hours, and continue declining logarithmically thereafter. The HACC102S80V500, with its paraelectric SiO₂ dielectric, has zero ferroelectric domains and therefore zero aging—capacitance measured at t=0 and t=10 years (87,600 hours) will be identical within measurement uncertainty. For aerospace and industrial systems with multi-decade service lives, this eliminates a critical long-term drift mechanism that would otherwise require periodic recalibration.
• No Hysteresis Loop: Ferroelectric dielectrics exhibit a characteristic polarization-versus-voltage (P-V) hysteresis loop analogous to the B-H loop of magnetic materials. In capacitor terms, this means the capacitance measured while increasing voltage differs from the capacitance measured while decreasing voltage—creating a history-dependent uncertainty band of 2–10% in ferroelectric MLCCs. The paraelectric SiO₂ in the HACC102S80V500 has no P-V hysteresis; capacitance is a single-valued function of the instantaneous voltage and temperature, regardless of prior bias history.

2. Ultra-Linear C-V Characteristics—Capacitance Independent of Applied Voltage

The capacitance of a ferroelectric MLCC decreases significantly under DC bias voltage—a phenomenon known as the DC bias coefficient or voltage coefficient of capacitance (VCC). Class II X7R dielectrics can lose 30–80% of their rated capacitance at the rated DC voltage. The HACC102S80V500 eliminates this degradation through the paraelectric nature of SiO₂:

• Ultra-Low VCC (<10 ppm/V): Unlike the barium titanate perovskite crystal structure, which changes its dielectric constant in response to an applied electric field (the electrostrictive effect), the amorphous SiO₂ dielectric constant of 3.9 is fundamentally independent of applied field. The measured VCC of <10 ppm/V means a 1000pF capacitor at 0V DC maintains 999pF at 80V DC—a change of less than 0.1%. This is a 300–800× improvement over X7R MLCCs.
• Predictable Circuit Behavior: In an RF power amplifier bias network, a decoupling capacitor that experiences 50% capacitance droop under the nominal bias voltage creates a resonance shift in the bias tee that can detune the matching network by hundreds of MHz at microwave frequencies. The HACC102S80V500's ultra-linear C-V characteristic eliminates this source of impedance uncertainty, enabling predictable circuit simulation and first-pass design success.
• No AC Amplitude Nonlinearity: In addition to DC bias effects, ferroelectric dielectrics exhibit capacitance variation with AC signal amplitude—the C-V curve is nonlinear even around the zero-bias point. This creates harmonic distortion: a sinusoidal voltage across a nonlinear capacitor generates harmonic currents. The paraelectric SiO₂ in the HACC102S80V500 has a linear dielectric response up to the dielectric breakdown field (>10MV/cm), meaning the capacitance is independent of AC signal amplitude for all practical RF power levels through the device.

Key Features

• Zero Dielectric Memory: Paraelectric SiO₂ dielectric with no ferroelectric domains eliminates dielectric absorption hysteresis, logarithmic aging, and P-V hysteresis. Dielectric absorption <0.1%, aging rate 0% per decade-hour.
• Ultra-Linear C-V Characteristics: Capacitance varies less than 0.1% from 0V to 80V rated DC voltage (<10 ppm/V VCC). No AC amplitude nonlinearity up to dielectric breakdown. 300–800× improvement over X7R MLCC.
• High Voltage Rating (80V DC): 300nm thermal SiO₂ dielectric provides >200V DWV (250% rated) with >10MV/cm intrinsic breakdown strength. Suitable for high-voltage bias networks in GaN power amplifiers.
• High Capacitance Density (1000pF): 1000pF in 0.75mm × 0.75mm footprint provides the highest capacitance available in the single-layer MOS platform—suitable for low-frequency bypass and coupling where MLCCs would introduce dielectric memory errors.
• Customizable Platform: Capacitance from 10pF to 1000pF across standard footprints from 0.50mm to 1.00mm. Custom voltage ratings, chip geometries, and metallization options available.

Electrical Specifications (T = 25°C unless noted)

Typical Applications

• Precision sample-and-hold (S/H) circuits where dielectric absorption directly limits measurement accuracy
• High-resolution ADC input filters where capacitor dielectric memory creates voltage-dependent offset errors
• GaN power amplifier high-voltage bias decoupling requiring both 80V rating and zero DC bias capacitance droop
• Precision analog filters (Bessel, Butterworth, elliptic) where capacitance tolerance and linearity define filter passband accuracy
• Charge-sensitive preamplifiers for radiation detectors where dielectric absorption creates baseline restoration errors
• Medical imaging and scientific instrumentation requiring multi-year calibration stability without capacitance drift

Assembly Quick Reference

• Die Attach: AuSn eutectic solder (300–320°C, N₂/H₂ forming gas) for lowest ground resistance. Conductive Ag epoxy (Epotek H20E, 120°C/30min) as alternative.
• Wire Bonding: 25µm Au thermosonic ball bonding (120–150°C stage, 15–35gf force, >6gf pull strength). Bond landing ≥25µm from electrode edge.
• Storage: Waffle pack or gel-pak, vacuum-sealed with nitrogen purge. MSL 1 unlimited floor life. Store at 20–25°C, 40–60% RH.

Ordering and Custom Configuration

Standard product ships as 0.75mm × 0.75mm square chips in conductive waffle packs. Custom configurations available with minimum order quantities starting at 10 pieces:

• Custom capacitance from 10pF to 1000pF on standard footprints (0.50mm–1.00mm)
• Voltage ratings from 6.3V to 100V DC
• Rectangular chip geometries up to 4:1 aspect ratio
• Alternative backside metallization for specific assembly processes

Contact us with your target specifications for a feasibility assessment and quotation. Standard 1000pF evaluation samples ship within 1–2 weeks.