MOS Capacitors 220 pF 100V High Breakdown Voltage Oxide Integrity Single Layer Chip with Custom Sizing

HACC221S100V240 - 220 pF 100 V Single-Layer MOS Capacitor with High Breakdown Voltage and Custom Die Sizing

Quick Answer

The HACC221S100V240 is a wire-bondable single-layer MOS capacitor rated 220 pF ±5% at 100 V DC, built on a 300 nm thermally grown SiO₂ dielectric over float-zone silicon. The standard die is 0.60 × 0.60 × 0.15 mm with a dielectric withstanding voltage above 250 V DC and leakage under 5 nA at 25 °C. Die outline, thickness, capacitance, metallisation and packaging are all re-specifiable, so the same design can be adapted to different substrates.

Oxide Integrity and Breakdown Voltage

In a MOS capacitor the reliability question is decided at the oxide interface, so the process and the screens are described here in full rather than summarised as a single claim.

• Grown dielectric. The 300 nm SiO₂ is thermally grown on the silicon surface rather than deposited or sintered, which gives a dense, stoichiometric film with a controlled interface state density. Metallisation is sputtered in the same vacuum sequence, so no organic or particulate contamination is trapped between oxide and electrode.
• Breakdown margin. Dielectric withstanding voltage exceeds 250 V DC, that is 250% of the 100 V rating, verified by a one-minute ramp test applied during production.
• Oxide screening. Lots are sampled for time-zero dielectric breakdown, with a target defect density below 1 per cm²; ramp-voltage screening removes units whose breakdown signature falls below the acceptance window.
• Leakage. Under 5 nA at 100 V DC and 25 °C, under 100 nA at 125 °C. For bias-tee and high-impedance amplifier nodes this keeps the noise floor stable over temperature.
• Life testing. 1000 h high-temperature reverse bias at 125 °C with 100 V applied, and 1000 h operating life with 100 V bias. Recorded capacitance drift is below 1% and leakage stays within twice the initial value.
• Environmental stress. 500 air-to-air cycles from -65 °C to +150 °C with no cracking, delamination or bond degradation, and die shear above 2.5 kgf after stress. 500 h at 85 °C / 85% RH with bias produces capacitance shift below 0.5%: the oxide absorbs no bulk water and the silver-free TiW-Au-Pt metallisation has no migration path.
• Moisture class. MSL 1 per J-STD-020, unlimited floor life at ≤30 °C / 85% RH, so no dry-pack tracking or baking step is required.

Custom Sizing and Packaging

The photolithography mask, dicing pitch, wafer thickness and back-end are configurable, so the capacitor can be made to fit the substrate instead of the layout being redesigned around a catalogue footprint.

Assembly compatibility. Die attach by AuSn 80/20 eutectic (280-320 °C) or silver-filled conductive epoxy such as Epotek H20E (150 °C cure). Interconnect by 25 µm gold thermosonic ball or wedge bonding, 25-33 µm aluminium ultrasonic wedge bonding at room temperature, or gold ribbon bonding. Recommended window for 25 µm gold wire: 25-35 gf force, 80-120 mW ultrasonic power, 120-150 °C stage temperature; keep the bond footprint at least 25 µm inside the electrode edge.

Typical Applications

• RF bias tees and power amplifier drain or gate bias injection networks
• Broadband DC blocking in hybrid microcircuits and multi-chip modules
• Aerospace and industrial electronics requiring long service life and low drift
• Downhole instrumentation, industrial sensors and equipment operating at elevated temperature
• Medical RF generators, MRI coil electronics and diagnostic front ends
• Outdoor wireless units, remote radio heads and base station front ends exposed to condensing humidity
• High-impedance sensor front ends, integrators and sample-and-hold stages