Symmetrical Dual-Polarity MOS Capacitor 470pF 100V High dV/dt Transient Immunity Single Layer Chip For RF Switching

HACC471S100V701 Symmetrical Dual-Polarity MOS Capacitor 470pF 100V Single Layer Wire Bondable RF Chip

Product definition: The HACC471S100V701 is a single-layer metal-oxide-semiconductor (MOS) capacitor built on a high-resistivity float-zone silicon substrate with a thermally grown silicon dioxide (SiO₂) dielectric. It delivers 470 pF (±10%) at a 100 V DC working voltage in a 0.50 mm × 0.50 mm × 0.15 mm wire-bondable chip. The same device family is also described as a single layer capacitor (SLC) chip, an RF chip capacitor, a wire bondable capacitor, or a MOS chip capacitor.

Its two defining characteristics are symmetrical dual-polarity operation and high dV/dt transient immunity. Together they make the part a good fit for bipolar and AC-coupled RF circuits in which the capacitor must behave identically for positive and negative signal excursions and must tolerate fast voltage ramps.

Key Features

Symmetrical Dual-Polarity Operation

In a conventional MOS capacitor the measured capacitance depends on the applied bias polarity: one polarity drives the silicon into accumulation (C ≈ Cox) while the opposite polarity drives it toward depletion, lowering the effective capacitance. The HACC471S100V701 uses a symmetrical metal-oxide-semiconductor platform with a degenerate, heavily doped float-zone silicon electrode so the semiconductor capacitance remains far above the oxide capacitance under both bias directions. The result is a near-identical C-V characteristic for positive and negative bias — capacitance holds within ±1% across ±100 V. This makes the device suitable for AC-coupled and bipolar signal paths where the capacitor must behave identically regardless of signal polarity, reducing waveform asymmetry and distortion.

High dV/dt Transient Immunity

A capacitor subjected to a fast voltage ramp draws a displacement current i = C · dV/dt. The single-layer construction removes the internal electrode stack of a multilayer ceramic capacitor, keeping the equivalent series inductance (ESL) below 0.05 nH and limiting the parasitic voltage overshoot generated during fast transients. Combined with the ≥2.5 µm gold metallization, which provides a robust, low-resistance current path and thermal mass, the HACC471S100V701 withstands rapid dV/dt events such as switching spikes and pulsed-RF envelopes. For a 470 pF device, a 1000 V/µs ramp produces roughly 0.47 A of displacement current, which the part handles without capacitive degradation or metal damage. The 100 V rating with a 250% dielectric withstanding voltage provides additional headroom.

Low Loss, Stable Over Frequency and Temperature

The SiO₂ dielectric shows a temperature coefficient of capacitance (TCC) of approximately +35 ppm/°C, nearly linear from -55°C to +125°C, and a low DC bias coefficient (<10 ppm/V). Q exceeds 2000 at 1 MHz and stays above 200 at 1 GHz, while dielectric absorption is typically below 0.05% — important for sample-and-hold and precision integrator stages.

Electrical Specifications (T = 25°C unless noted)

Reliability and Qualification (typical values)

Typical Applications

• Bipolar and AC-coupled RF signal paths requiring identical behavior in both polarities
• DC blocking and impedance matching in push-pull amplifiers and differential front-ends
• High-speed switching nodes and pulsed-RF stages exposed to fast dV/dt transients
• RF bypass and supply decoupling where low ESL and stable capacitance are required
• VCO tank circuits and filter networks from 100 MHz to 6 GHz