Ultra Low ESR Fine Capacitance Step Wire Bond Capacitor Precision Tuning High Capacitance Capacitor For Multi Gigabit

Custom MOS Capacitor Ultra Low ESR Multi Gigabit Fine Capacitance Step Precision Tuning Wire Bond Optimized Surface

HACC-CUSTOM-ES: Ultra-Low ESR MOS Capacitor for Multi-Gigabit SERDES with Fine Capacitance Step & Wire-Bond Optimized Surface

Engineered Ultra-Low ESR for Multi-Gigabit Links

Multi-gigabit SERDES (Serializer/Deserializer) DC blocking capacitors face stringent equivalent series resistance (ESR) requirements. At 10 Gbps and beyond, even 0.1 Ohm of ESR contributes to insertion loss, eye closure, and deterministic jitter. The HACC-CUSTOM-ES achieves ESR <0.05 Ohm at 10 GHz and <0.02 Ohm at 40 GHz through three concurrent design optimizations:

• 3–5µm thick gold top electrode: Reduced sheet resistance minimizes skin-effect contribution at microwave frequencies, maintaining low ESR across the multi-gigabit Nyquist bandwidth.
• Multi-finger electrode layout: Parallel current paths distribute RF current, eliminating current crowding at electrode edges — the primary ESR failure mechanism in single-finger designs.
• Low-resistivity substrate (N+ Si, <0.01 Ohm·cm): Minimizes series resistance in the semiconductor region, ensuring the substrate is not the ESR bottleneck.

ESR is verified per frequency band: <0.05 Ohm from 1–10 GHz, <0.1 Ohm from 10–20 GHz, and <0.15 Ohm from 20–40 GHz — providing designers with guaranteed ESR margins for their specific SERDES data rate.

Ultra-Fine Capacitance Step & Precision Value Tuning

High-speed serial link tuning requires precise capacitance values — not just within a tolerance band, but at the exact value optimized through simulation. The HACC-CUSTOM-ES offers capacitance step of 1 pF minimum increment with laser-trimmable resolution to 0.1 pF, achieving ±2% of the target value. Available in a fine-step series (1p, 2p, 3p, 5p, 7p, 10p, 15p, 22p, 33p, 47p, 68p, 100p) from 0.5 pF to 1000 pF. Each die undergoes in-situ capacitance measurement with closed-loop laser trim feedback, and S-parameter verification post-trim confirms the capacitance value in the actual RF environment — not just at 1 MHz LCR meter frequency.

Wire-Bond Optimized Surface Metallization

Wire bond reliability in high-speed assemblies is determined by the top metallization quality. The HACC-CUSTOM-ES features 3µm thick gold surface metallization with <50 nm Ra surface roughness and controlled grain structure — achieving pull strength exceeding 3.0 g on both 25µm and 18µm wire diameters, compatible with both wedge and ball bonding processes. The controlled surface minimizes bond deformation variability and ensures consistent electrical contact impedance across all bonds in a multi-die module.

Key Specifications

Applications

• PAM4/NRZ SERDES DC Blocking — ESR <0.05 Ohm for 56/112 Gbps eye margin, multi-finger uniform current distribution
• Transimpedance Amplifier (TIA) Bias Filtering — 0.1 pF laser-trim accuracy, S-parameter verified post-trim for exact filter pole placement
• High-Speed Photonics Module Interposers — 3µm Au wire-bond optimized, AuSn eutectic compatible, 50nm Ra surface for consistent bond impedance
• Coherent Optical DSP Bias Networks — 1 pF fine-step series from 0.5 pF–1000 pF, precision value tuning to ±2% for exact DSP tap weight capacitance

Contact us with your target ESR, capacitance value, and wire bond requirements. Custom ultra-low ESR MOS capacitors with precision step tuning ship in 5–7 business days.