| Brand Name: | Hoan |
| Model Number: | HACC101S50V200 |
| MOQ: | 100 Pieces |
| Payment Terms: | T/T,L/C,D/P,D/A |
The HACC101S50V200 is a wire-bondable single-layer MOS capacitor: 100 pF ±1% at 50 V DC, built on a 300 nm thermally grown SiO₂ dielectric over float-zone silicon. The chip measures 0.50 × 0.50 × 0.15 mm and shows typically 0.05 nH intrinsic ESL, under 0.2 Ω ESR at 1 GHz, and a self-resonant frequency above 2 GHz when mounted with a 0.5 mm gold bond wire. Capacitance, footprint, thickness, metallisation and packaging can all be re-specified per order.
| Item | Value |
| Capacitance | 100 pF ±1% (1 MHz, 1.0 Vrms, 25 °C) |
| Rated DC voltage | 50 V continuous |
| Dielectric withstanding voltage | >125 V DC (1 minute, production screened) |
| Dielectric | Thermal SiO₂, 300 nm, grown on float-zone Si |
| Intrinsic ESL | <0.05 nH typical (de-embedded) |
| ESR | <0.2 Ω typical at 1 GHz |
| Q factor | >2000 at 1 MHz typical |
| Self-resonant frequency | >2 GHz typical, 0.5 mm gold bond wire |
| Chip size | 0.50 × 0.50 × 0.15 mm (±0.015 mm) |
| Termination | TiW-Au top (≥2.5 µm Au), TiW-Pt-Au backside |
| Operating temperature | -55 °C to +125 °C |
The mask set, dicing pitch, wafer thickness and back-end packaging are configurable, so the capacitor can be fitted to the substrate instead of the layout being redesigned around a catalogue part.
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