| Brand Name: | Hoan |
| Model Number: | HACC470S50V160 |
| MOQ: | 10 Pieces |
| Payment Terms: | L/C,D/A,D/P,T/T,Western Union |
The HACC470S50V160 is a 47pF ±10% single-layer MOS capacitor rated at 50V DC, fabricated on high-resistivity float-zone silicon (>1000 Ω·cm) with 300nm thermally-grown amorphous SiO₂ dielectric. With an ultra-miniature footprint of just 0.40 * 0.40 * 0.15mm (16mil * 16mil * 6mil) — a 36% area reduction versus standard 0.50mm chips — this device enables capacitor integration into the most extreme space-constrained RF hybrid microcircuits, phased-array beamformer tiles, and satellite payload modules where every square micron of carrier real estate is critical.
At 0.40 * 0.40mm, the HACC470S50V160 occupies just 0.16mm² of carrier area — compared to the standard 0.50mm MOS capacitor footprint (0.25mm²). The 0.15mm (6mil) ultra-low profile is half the height of a standard 0402 MLCC (0.30mm profile) and fits within the tightest hermetic module lid clearances. This extreme miniaturization is achieved through advanced photolithography electrode definition on the single-layer MOS platform. Despite the compact size, the 2.5µm minimum gold top electrode provides a reliable wire bond pad with >6gf pull strength (25µm Au wire, thermosonic ball bonding), and the top ceramic border margin provides a clear optical reference for automated wire bonder vision systems. The full perimeter un-metallized margin is an integral ceramic feature — not an applied coating — and cannot be scratched, dissolved, or thermally degraded.
Piezoelectric noise in capacitors is a well-documented failure mechanism in vibration-exposed electronics: mechanical strain induces a voltage through the direct piezoelectric effect (strain → polarization), modulating capacitance and introducing spurious signals into sensitive RF paths. The HACC470S50V160 eliminates this mechanism at the material level through its amorphous SiO₂ dielectric:
Total Ionizing Dose (TID) radiation degrades standard MOS structures through interface trap generation and fixed oxide charge accumulation, which shift threshold voltage and cause capacitance drift. The HACC470S50V160 uses a radiation-hardened nitrided SiO₂ gate oxide formulation specifically designed to minimize these effects:
| Parameter | Value | Condition |
|---|---|---|
| Capacitance | 47pF ±10% | 1MHz, 1.0Vrms |
| Available Tolerances | ±10% (K), ±5% (J) | — |
| Rated DC Voltage | 50V | Continuous |
| Dielectric Withstanding Voltage | >125V (>2.5* rated) | 5 sec dwell, 100% test |
| TID Hardness | >100 krad(Si) | ESCC 22900 |
| Q Factor @ 1MHz / @ 1GHz | >2000 / >200 | Typical |
| ESR @ 1GHz | <0.1 Ω | De-embedded |
| Intrinsic Chip ESL | <0.05nH | De-embedded from S-parameter |
| Leakage @ 25°C / @ 125°C | <10nA / <100nA | 50V DC |
| TCC | 0 ±30 ppm/°C | -55°C to +125°C |
| Piezoelectric Output | Below noise floor | 10g, 20Hz–2kHz sweep |
| Dielectric | Thermal SiO₂, 300nm | Amorphous, zero piezoelectric |
| Substrate | Float-zone Si, >1000 Ω·cm | — |
| Chip Dimensions | 0.40 * 0.40 * 0.15mm | ±15µm tolerance |
| Top Metallization | TiW-Au, 2.5µm min Au | — |
| Backside Metallization | TiW-Pt-Au, 1.0µm min Au | Pt barrier for Ag epoxy |
| Operating / Storage Temp | -55 to +125°C / -65 to +150°C | — |
| RoHS | Compliant (EU 2015/863) | Halogen-free per IEC 61249-2-21 |
Contact us for evaluation samples with full S-parameter data (1–20GHz), TID radiation test reports per ESCC 22900, vibration test data per IEC 60749, or custom capacitance values on the 0.40mm ultra-small platform.