Ultra Low Noise MOS Capacitor HACC101S30V220 22pF 30V Hot Carrier Noise Control for LNA

Ultra Low Noise MOS Capacitor HACC101S30V220 22pF 30V

Summary: The HACC101S30V220 is a 22 pF ±10%, 30 V DC single-layer MOS (metal-oxide-semiconductor) capacitor built on a float-zone silicon substrate with a 300 nm thermal SiO₂ dielectric. It is designed for ultra-low noise amplifier (LNA) input matching and DC blocking, where component noise and interface behaviour determine the receiver noise figure.

Overview

The HACC101S30V220 uses a single-layer MOS structure instead of a multilayer ceramic stack. The chip measures 0.50 × 0.50 × 0.15 mm with 2.5 µm minimum gold top metallization and 1.0 µm minimum backside gold. It is wire bondable and compatible with eutectic die attach, and is offered in standard ±10% (K) and ±5% (J) capacitance tolerances.

Key Features

• Hot-carrier thermal noise control: intrinsic chip ESL below 0.05 nH with low interface trap density.
• Hot-carrier noise suppression: no piezoelectric or microphonic output.
• 22 pF ±10% (5% available) at 30 V DC with no DC bias capacitance derating.
• Q > 2000 at 1 MHz and > 300 at 1 GHz; ESR below 0.1 Ω at 1 GHz.
• Float-zone silicon substrate above 1000 Ω·cm for low substrate loss.
• TiW-Au top electrode and TiW-Pt-Au backside for wire bond and eutectic die attach.
• Available in custom capacitance values on the same 0.50 mm platform.

Electrical Specifications (T = 25°C unless noted)

Typical Applications

• Ultra-low noise amplifier (LNA) input matching and DC blocking
• Low phase noise VCO and PLL oscillator tank circuits
• RF receiver front ends and array beamformer modules
• Low-noise bias injection and power supply decoupling
• Noise-sensitive test and measurement instrumentation