Ultra High SRF 100pF 25V MOS Capacitor Conductive Silicon Substrate Direct Grounding Single Layer RF Chip

HACC101S25V500 Ultra-High Self-Resonant Frequency MOS Capacitor: 100pF 25V with Conductive Silicon Substrate for Direct Grounding

The HACC101S25V500 is a 100pF ±10% single-layer MOS capacitor rated at 25V DC, fabricated on conductive float-zone silicon (>1000Ω·cm) with 300nm thermally-grown SiO₂ dielectric. Chip dimensions are 0.50mm × 0.50mm × 0.15mm with TiW-Au top metallization (2.5µm minimum Au) and TiW-Pt-Au backside (1.0µm minimum Au). This device is engineered for applications demanding the highest possible self-resonant frequency and the lowest ground inductance through direct conductive substrate grounding. Fully customizable: capacitance from 10pF to 220pF, voltage ratings from 6.3V to 50V, custom chip geometries, and alternative backside metallization options available with 3-4 week prototyping lead time.

1. Ultra-High Self-Resonant Frequency Through Minimal Parasitic Inductance

The self-resonant frequency (SRF) of a capacitor—the frequency at which parasitic series inductance resonates with the capacitance, above which the component behaves inductively—determines the maximum usable frequency for bypass and coupling applications. The HACC101S25V500 achieves an exceptionally high SRF through its single-layer architecture and optimized electrode geometry:

• Chip-Level SRF: >10GHz (de-embedded, no bond wire). Achieved through optimized electrode aspect ratio and minimized current path length—substantially higher than standard MOS capacitors in the same capacitance range.
• System SRF (0.5mm bond wire): >1.5GHz with a single 25µm Au wire. For applications requiring SRF above 3GHz, two parallel bond wires halve the effective inductance to ~0.2nH, pushing system SRF beyond 2.5GHz.
• MLCC Comparison: A typical 100pF MLCC in 0402 package has an ESL of approximately 0.4–0.6nH—an order of magnitude higher than the intrinsic chip ESL of the HACC101S25V500 (<0.03nH). The MLCC's SRF is therefore limited to approximately 600–800MHz. For applications above 5GHz—including 5G FR2 mmWave, satellite communication Ku/Ka-band, and automotive radar—the single-layer MOS capacitor provides a decisive advantage in usable bandwidth.

2. Conductive Silicon Substrate for Direct Grounding

Traditional chip capacitors require a separate ground bond wire or via to establish the ground connection, adding parasitic inductance that degrades high-frequency performance. The HACC101S25V500 leverages the inherently conductive nature of its float-zone silicon substrate to enable direct backside grounding:

• Conductive Substrate Physics: The float-zone silicon substrate with >1000Ω·cm resistivity provides sufficient conductivity for RF grounding while maintaining the high Q factor characteristic of low-loss substrates. The backside TiW-Pt-Au metallization forms a low-resistance contact to the silicon, enabling direct electrical connection from the capacitor's ground plane to the carrier ground pad through the die-attach interface.
• Ground Inductance Elimination: In a conventional chip capacitor assembly, the ground bond wire adds approximately 0.3–0.5nH of inductance. For a 100pF device at 10GHz, this additional 0.5nH increases the impedance from the ideal 0.16Ω to approximately 31Ω—a 200× degradation. By eliminating the ground bond wire and routing the ground current directly through the conductive substrate and die-attach interface, the HACC101S25V500 reduces the total ground-path inductance to below 0.05nH.
• Die-Attach Ground Interface: When attached with AuSn eutectic solder (280°C, forming gas), the ground contact resistance is below 5mΩ. Conductive silver epoxy (Epotek H20E, 120°C cure) provides an alternative with approximately 10–20mΩ ground contact resistance.

3. Design Optimization for Maximum SRF

Achieving chip-level SRF beyond 10GHz requires attention to every contributor to parasitic inductance:

• Electrode Aspect Ratio Optimization: The square 0.50mm × 0.50mm outline provides a uniform current distribution from the bond pad to the dielectric, eliminating the current crowding at electrode edges that generates localized inductance in rectangular or irregular electrode designs.
• Thick Gold Metallization: The 2.5µm minimum gold top electrode provides low sheet resistance (<30mΩ/sq), minimizing the resistive contribution to impedance at microwave frequencies. At 10GHz, the skin depth in gold is approximately 0.8µm—the 2.5µm thickness ensures the entire RF current flows within the low-resistance gold layer.
• Minimized Bond Pad Capacitance: The bond pad area is optimized to balance wire-bond reliability (minimum 80µm × 80µm for 25µm wire) against parasitic pad-to-substrate capacitance, preventing excess area from shifting the SRF lower.

Key Features

• Ultra-High Self-Resonant Frequency: Chip-level SRF >10GHz (de-embedded), system SRF >1.5GHz with single 0.5mm bond wire. Multi-parallel bond wires or ribbon bonding push system SRF beyond 2.5GHz. 20× higher SRF than equivalent-capacitance 0402 MLCC.
• Conductive Substrate Direct Grounding: Float-zone silicon substrate enables direct backside ground connection through die-attach interface. Eliminates ground bond wire inductance (~0.5nH). Total ground-path inductance <0.05nH.
• Ultra-Low ESL Architecture: Intrinsic chip ESL <0.03nH achieved through single-layer coaxial current path, optimized electrode aspect ratio, and thick gold metallization. ESL is 15–20× lower than equivalent-capacitance MLCC.
• SiO₂ Dielectric Stability: Thermal SiO₂ with near-zero dielectric heating (tan δ <0.001 at 1GHz), +35ppm/°C TCC, and zero ferroelectric aging. No capacitance droop under DC bias.
• Customizable Platform: Capacitance from 10pF to 220pF on standard 0.50mm footprint. Custom chip geometries (rectangular up to 4:1 AR), voltage ratings, and backside metallization options available.

Electrical Specifications (T = 25°C unless noted)

Typical Applications

• 5G FR2 mmWave (24–52GHz) phased-array beamformer DC blocking and inter-stage coupling requiring SRF well above the operating band
• Satellite communication Ku-band (12–18GHz) and Ka-band (26–40GHz) payload bypass networks where ground inductance directly limits decoupling effectiveness
• Automotive radar (76–81GHz) MMIC bias networks requiring near-ideal capacitive behavior through the full operating frequency range
• High-speed SERDES (112Gbps PAM4) DC blocking where capacitor parasitic inductance creates eye-closing impedance discontinuities
• RF power amplifier matching networks above 5GHz where MLCC self-resonance renders the component unusable
• Microwave point-to-point radio (6–42GHz) bypass applications where every 0.1nH of ground inductance degrades link budget

Assembly Quick Reference

• Die Attach: AuSn eutectic solder (300–320°C, N₂/H₂ forming gas) for lowest ground resistance and thermal resistance. Conductive Ag epoxy (Epotek H20E, 120°C/30min) as alternative. Direct grounding through backside metallization eliminates need for separate ground bond wire.
• Wire Bonding: 25µm Au thermosonic ball bonding (120–150°C stage, 15–35gf force, >6gf pull strength). For SRF >2.5GHz, use two parallel 25µm bond wires or 25µm × 75µm Au ribbon. Bond landing ≥25µm from electrode edge.
• Storage: Waffle pack or gel-pak, vacuum-sealed with nitrogen purge. MSL 1 unlimited floor life. Store at 20–25°C, 40–60% RH.

Ordering and Custom Configuration

Standard product ships as 0.50mm × 0.50mm square chips in conductive waffle packs. The following custom configurations are available on request with minimum order quantities typically starting at 10 pieces:

• Custom capacitance values within the 10pF–220pF range on the standard 0.50mm platform
• Rectangular chip geometries up to 4:1 aspect ratio
• Non-standard voltage ratings from 6.3V to 50V DC
• Alternative backside metallization: Au-only (for dedicated AuSn eutectic), AuSn pre-deposition (3–5µm), or Al for specific process flows
• Gel-pak or tape-and-reel packaging for automated assembly

Contact us with your target specifications for a feasibility assessment, lead time estimate, and quotation. Standard 100pF evaluation samples ship within 1–2 weeks. Custom configurations with 3–4 week prototyping lead time.