| Brand Name: | Hoan |
| Model Number: | HACC471S20V500 |
| MOQ: | 10 Pieces |
| Payment Terms: | L/C,D/A,D/P,T/T,Western Union |
The HACC471S20V500 is a high-performance, fully customizable Single Layer MOS capacitor fabricated on high-resistivity float-zone silicon substrate (>1000 Ohm·cm) with 300nm thermally-grown SiO2 dielectric. Rated at 470pF ±10% with 20V DC continuous operating voltage, this device combines High Q factor, Ultra-Low ESL/ESR, Exceptional Capacitance Stability, and Wire-Bondable Top Contact in a compact 0.50*0.50*0.15mm chip-scale package. The Double-Sided Bordered (Margin) architecture prevents conductive epoxy shorts during die attach while providing a clear visual reference for automated wire bonder alignment. Available as a standard catalog product with full customization options for capacitance value, tolerance, voltage rating, chip geometry, and backside metallization to match your specific RF circuit requirements.
The single-layer coaxial current path architecture fundamentally eliminates the parasitic inductance and resistance mechanisms that degrade MLCC performance at GHz frequencies. Current flows vertically from the top gold electrode through the SiO2 dielectric to the backside ground plane — a path length of just 0.15mm with no internal electrodes, no vias, and no serpentine routing.
At gigahertz frequencies, capacitor Q becomes the dominant loss mechanism in impedance matching networks. The HACC471S20V500's ultra-low ESR ensures that in a 5G n77 (3.3-4.2GHz) power amplifier output match, the capacitor recovers 0.3-0.8dB of through-loss per matching element compared to an equivalent-capacitance MLCC — a critical advantage for meeting transmitter efficiency targets.
Class I COG/NPO (C0G/NP0) paraelectric ceramic dielectric provides consistent stability under all operating conditions:
For bias tee, VCO tank, and active bias network designs, this stability eliminates the need for complex temperature compensation varactor tuning and bias-dependent capacitance derating tables.
The top electrode features an advanced multi-layer sputtered thin-film metallization stack — TaN/TiW/Ni/Au with minimum 2.5µm gold thickness — engineered specifically for reliable, high-yield thermosonic wire bonding:
The Double-Sided Bordered architecture places an un-metallized ceramic margin around both top and bottom electrodes, providing epoxy containment during die attach and a clear optical reference for automated bonding — eliminating orientation requirements during pick-and-place.
The HACC471S20V500 is built on a configurable MOS capacitor platform. We offer full customization of the following parameters with rapid prototyping turnaround:
| Parameter | Standard Value | Custom Range |
|---|---|---|
| Capacitance | 470pF ±10% | 10pF – 1000pF; ±5% tolerance available |
| Rated Voltage | 20V DC | 6.3V – 100V DC |
| Dielectric Type | COG/NPO (Class I) | X7R (Class II) or custom high-K |
| Chip Dimensions | 0.50*0.50*0.15mm | 0.25*0.25mm to 5.0*5.0mm; rectangular up to 4:1 AR |
| Top Metallization | TaN/TiW/Ni/Au, 2.5µm Au | Up to 5.0µm Au for heavy wire bonding |
| Backside Metallization | TiW-Pt-Au, 1.0µm Au | Au-only, AuSn pre-deposition (3-5µm), or Al |
| Design Architecture | Double-Sided Bordered | Single-Sided Bordered or borderless |
| Prototype Lead Time | 3-4 weeks | Expedited 1-2 weeks available |
| Parameter | Value | Test Condition |
|---|---|---|
| Nominal Capacitance | 470pF ±10% | 1MHz, 1.0Vrms, 25°C |
| Rated DC Voltage | 20V | Continuous, -55°C to +125°C |
| Dielectric Withstanding Voltage | >50V (250% rated) | 5 sec dwell, 100% production test |
| Q Factor @ 1MHz | >2000 | Typical |
| Q Factor @ 1GHz | >200 | Typical |
| ESR @ 1GHz | <0.1 Ohm | De-embedded |
| Intrinsic Chip ESL | <0.05nH | De-embedded from S-parameter |
| Dissipation Factor | ≤0.15% | 1kHz, 1.0Vrms |
| Leakage Current @ 25°C | <10nA | 20V DC |
| TCC | 0 ±30 ppm/°C | -55°C to +125°C, COG/NPO |
| Chip Dimensions | 0.50 * 0.50 * 0.15mm | ±25µm tolerance |
| Operating Temperature | -55°C to +125°C | Full parametric compliance |
| Moisture Sensitivity | MSL 1 | Unlimited floor life per J-STD-020 |
Contact us today with your target specifications. Standard 470pF evaluation samples ship within 1-2 weeks. Custom capacitance values, voltage ratings, chip geometries, and metallization options available with 3-4 week prototyping lead time. Full RoHS, REACH, and halogen-free compliance documentation provided per production lot.