HongAn Microwave Co., Ltd.
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| Brand Name: | Hoan |
| Model Number: | HACC101S30V101 |
| MOQ: | 10 |
| Payment Terms: | Western Union,T/T,D/P,D/A,L/C |
HACC101S30V101 Double-Sided Bordered SLC 100pF 100V (0.05-15GHz)
High-Frequency Technical Summary
The HACC101S30V101 is a high-performance, symmetrical Double-Sided Bordered Single Layer Ceramic Capacitor (SLC). This model is engineered for broadband DC blocking, RF coupling, and bypass filtering up to 15.0 GHz (covering UHF, L, S, C, X, and Ku microwave bands). With a stable 100 pF ± 20% capacitance, a larger 0.76 mm × 0.76 mm footprint, and a high-voltage rating of 100 V, this capacitor is highly suitable for high-density Tactical radar subassemblies, fiber-optic transceivers, and microwave hybrid microcircuits.
What sets the HACC101S30V101 apart is its symmetrical double-sided bordered architecture combined with a larger 30 mil × 30 mil footprint. This symmetric structure eliminates top/bottom orientation requirements during pick-and-place, which significantly boosts automated assembly throughput and eliminates manual flipping errors.
Key Performance Advantages
Symmetrical Double-Sided Border (DSB): Eliminates top-vs-bottom mounting orientation issues, enabling ultra-fast automated die attachment and picking.
Dual-Side Epoxy Climb Protection: The ceramic border margins on both top and bottom electrodes act as a physical dam to stop conductive silver epoxy from climbing the sidewall, preventing short-circuits.
Advanced Thin-Film Metallization System: Utilizes a highly robust TaN/TiW/Ni/Au thin-film stack on both faces, offering exceptional thermal stability, anti-migration protection, and resistance to solder leaching.
100V Rated Voltage: Delivers higher voltage handling capacity in a robust 30 mil × 30 mil (0.76 mm × 0.76 mm) footprint, maintaining low dielectric dissipation.
High Shear Strength & Thermal Dissipation: The larger 30 mil mounting base provides greater bonding contact area, yielding exceptionally high mechanical shear strength and enhanced heat dissipation.
Overall Dimensions
Comprehensive Parameter Datasheet
| Specifications Category | Technical Parameter Name | Guaranteed Values | Testing / Measurement Conditions |
| Electrical Specs | Nominal Capacitance | 100 | pF (+20% Tolerance @ 1kHz,1Vrms, 25°C) |
| Rated Working Voltage (DC) | 100 | V (Maximum continuous rating) | |
| Dissipation Factor (DF) | ≤1.5% | Tested at 1 kHz, 1.0 Vrms, 25°C | |
| Insulation Resistance (IR) | ≥104MΩ | Tested at rated voltage DC, 25°C | |
| Recommended Frequency Band | 0.05 -15.0 | GHz (Broadband Coupling and Bypass Filtering) | |
| Physical Geometry | Outline Dimensions | 0.76 x 0.76 x 0.15 | mm (Length x Width x Height/30x 30x6mil) |
| Design Architecture | Double-Sided Bordered | Equal bare ceramic margin borders on both faces | |
| Metallization Stack | Top & Bottom Metallurgy | TaN/TiW/Ni/Au | Symmetrical thin-film stack on both surfaces |
| Outer Gold Thickness (Au) | ≥2.5 | um (Minimum thickness, wire-bond optimized) | |
| Assembly Processes | Mount Adhesion | Conductive Epoxy / Solder | Suitable for silver epoxy H20E /AuSn eutectic |
| Interconnect Connection | Gold Wire / Ribbon Bond | Thermosonic gold wire bonding compatible | |
| Reliability & Quality | Operating Temperature | -55 to +125 | ℃ (Industrial & Tactical Grade) |
| Storage Temperature & RH | 20-25°C,40%-60% RH | Cleanroom environment | |
| Guaranteed Shelf Life | 1 | Year (Under optimal storage conditions) |
Symmetrical Thin-Film Metallization Stack Engineering
To ensure long-term reliability under Tactical-grade thermal cycling and high-humidity conditions, theHACC101S30V101 utilizes a symmetrical, vacuum-sputtered thin-film stack on both top and bottom:
| Metal Layer | Material | Standard LayerThickness | Metallurgical Function & Engineering Value |
| Adhesion Layer | Tantalum Nitride (TaN) | Sputtered Base | Provides a highly stable, oxygen-blocking chemical bondto the ceramic substrate; prevents peeling under thermal stress. |
| Barrier Layer | Titanium-Tungsten (TiW) | Sputtered Barrier | Acts as a high-density diffusion barrier that prevents nickel and gold atoms from migrating into the ceramic dielectric. |
| Barrier Layer | Nickel (Ni) | Sputtered Sacrificial | Serves as a solder leach-resistant barrier; prevents gold leaching or scavenging during high-temperature solderreflow. |
| Bonding Finish | Gold (Au) | ≥2.5 µm | Provides a highly conductive, oxide-free surfaceoptimized for both gold wire thermosonic bonding andsilver-filled epoxy attachment. |
Comparative Technical Matrix (HACC101S30V101 vs. Other SLC Designs)
This matrix compares the assembly and electrical performance of different single-layer ceramic capacitor designs:
| Engineering Parameter | Double-Sided Bordered (HACC101S30V101) | Single-Sided Bordered SLC | Standard Borderless SLC |
| Symmetry (Orientation) | Symmetrical. Top and bottomare identical. No flipping needed. | Asymmetric. Must verifytop/bottom side beforemounting. | Asymmetric. Must verifytop/bottom side beforemounting. |
| Top Side Epoxy Safety | Outstanding. Bare ceramicmargin stops epoxy shortingtop surface. | Outstanding. Bare ceramic margin stopsepoxy shorting top surtace. | Poor. Gold covers 100%of top, leading to highrisk of surface shorts. |
| Bottom Side Epoxy Safety | Outstanding. Exposed ceramicborder halts epoxy climb at thebase. | Moderate. Bottom gold covers 100% of the base; epoxy climbs easily. | Poor. Solder/epoxy caneasily climb up the rawside walls. |
| Automated Assembly Speed | Maximum. High-speed pick-and-place with no visualorientation checking. | Medium. Automation requires camera inspection to detect top/bottom. | Medium. Requires vision inspection to orient before placement. |
| Solder Leach Resistance | Excellent (Ni-Au Finish). | Moderate to Good (Depending on barrier). | Moderate to Good (Depending on barrier). |
FAQ
Q1: What are the main benefits of a double-sided bordered design over a single-sided bordered design?
A:The primary benefit is symmetrical automation. With a single-sided bordered capacitor, assembly robots must use optical recognition to identify the top (bordered) surface and bottom (non-bordered) surface before placement. If placed upside down, the capacitor will fail. The HACC101S30V101 has identical bordered electrodes on both the top and bottom. It can be picked up, placed, and bonded from either side, which completely eliminates orientation errors and dramatically accelerates automated production lines.
Q2: How does the TaN/TiW/Ni/Au thin-film system prevent solder leaching?
A:During eutectic gold-tin (Au-Sn) soldering, molten solder easily "scavenges" or leaches pure gold electrodes, dissolving thin gold layers and causing electrical open-circuits. The HACC101S30V101 contains a dense Nickel (Ni) barrier layer beneath the gold surface. The Ni layer acts as a robust barrier that prevents the solder from leaching into the underlying TiW and TaN films, maintaining electrode integrity even during high-temperature reflow.
Q3: What is the recommended frequency limit for the HACC101S30V101?
A:This capacitor is highly optimized for 0.05 GHz to 15.0 GHz (Ku-band). Thanks to its single-layer construction, it exhibits virtually zero parasitic inductance and a much higher self-resonant frequency (SRF) compared to multi-layer ceramic capacitors (MLCCs). This ensures a flat, low-insertion-loss insertion curve throughout the entire frequency band.
