10pF 50V Bordered Single Layer Capacitor Millimeter Wave 5G E Band Capacitor For High Frequency

High-Frequency Technical Summary

The HACC100S15V500 is an ultra-low-capacitance, ultra-miniature Single-Sided Bordered Single Layer Ceramic Capacitor (SLC) purpose-engineered for millimeter-wave DC blocking and inter-stage coupling at the highest commercial communication frequencies. Delivering 10 pF ±10% with a 50 V DC rating, this capacitor is fabricated in a 15 mil × 15 mil (0.38 mm × 0.38 mm) footprint with an ultra-low 0.15 mm (6 mil) profile. With class-leading ESR <0.10 Ω at 10 GHz, ESL <25 pH, and self-resonant frequency >45 GHz (extending to >60 GHz with flip-chip mounting), the HACC100S15V500 behaves as a near-ideal, transparent series element for DC blocking from 1 GHz to beyond 50 GHz—covering 5G FR2 bands (n257, n258, n259, n260, n261, n262), 60 GHz WiGig (802.11ad/ay), E-band point-to-point backhaul (71-86 GHz), and automotive sensing (76-81 GHz).

Fabricated with Class I COG/NPO paraelectric ceramic dielectric, this capacitor maintains ±0.3% capacitance variation from -55°C to +125°C with zero DC bias voltage coefficient (<10 ppm/V)—eliminating the capacitance derating that plagues X7R dielectrics under bias. The single-layer coaxial electrode geometry eliminates the internal electrode resistance and via inductance of multi-layer capacitors, producing the lowest ESR/ESL of any ceramic capacitor technology. The ultra-low 0.15 mm height enables integration into the thinnest antenna-in-package (AiP) modules and 2.5D/3D heterogeneous integrated packages where interposer cavity depth limits component Z-height to <200 μm.

Key Performance Advantages

Ultra-Low ESR/ESL for mmWave — <0.10 Ω ESR, <25 pH ESL, >45 GHz SRF

At millimeter-wave frequencies, every femtohenry of parasitic inductance and every milliohm of series resistance directly degrades RF performance. The HACC100S15V500's single-layer coaxial structure—a straight vertical current path from top Au bond pad through the 0.15 mm COG/NPO dielectric to the bottom Au ground plane—achieves parasitic values that multi-layer capacitors cannot approach:

• ESR <0.10 Ω at 10 GHz: In a 28 GHz 5G n257 band LNA input DC block, this translates to <0.05 dB insertion loss contribution—essentially transparent to the RF signal path. An equivalent 0402 COG MLCC at 10 pF would contribute 0.3-0.5 dB insertion loss due to 10-20× higher ESR (1-2 Ω from nickel internal electrodes). In a 4-stage LNA with 3 inter-stage DC blocks, the cumulative noise figure improvement from using HACC100S15V500 vs. MLCC is approximately 0.3-0.5 dB—equivalent to increasing the LNA gain by 7-12%.
• ESL <25 pH: With 25 pH series inductance, the inductive reactance (jωL) at 50 GHz is only j7.9 Ω—negligible compared to the capacitive reactance (-j318 Ω for 10 pF). This means the capacitor behaves as a pure capacitor through 50 GHz with no inductive contribution to phase shift or impedance transformation. Compare to an 0402 MLCC with 300-500 pH ESL: at 28 GHz, the MLCC's inductive reactance (j53 Ω at 300 pH) is already comparable to the capacitive reactance (-j57 Ω), causing the capacitor to behave as an inductor above its ~4 GHz SRF—completely unusable for mmWave DC blocking.
• SRF >45 GHz (wire bond), >60 GHz (flip-chip): The self-resonant frequency—where the capacitor transitions from capacitive to inductive behavior—is well above the highest 5G FR2 frequency (52.6 GHz for n262) and usable through E-band (71-86 GHz) with flip-chip mounting. This is possible because the single-layer structure has zero internal electrode layers, zero internal vias, and zero internal electrode edge parasitics—the ESL is determined solely by the external bond wire or flip-chip bump, not by internal geometry.
• Negative insertion loss slope: As frequency increases from 1 GHz to 50 GHz, the SLC's insertion loss (S21) actually decreases—from ~0.15 dB at 1 GHz to <0.05 dB at 40 GHz—because the capacitive reactance decreases with frequency while the ESR remains nearly constant. This is the opposite of MLCC behavior, where S21 degrades sharply above SRF.

Low-Profile & Ultra-Miniaturization — 0.15 mm Height for Antenna-in-Package Integration

5G mmWave antenna-in-package (AiP) modules and 2.5D silicon interposer assemblies impose extreme Z-height constraints. A typical AiP cavity depth between the interposer surface and the antenna substrate is 180-250 μm—and the capacitor plus its bond wire loop must fit entirely within this space. The HACC100S15V500's 0.15 mm (150 μm) die height leaves 30-100 μm of headroom for the 25 μm Au bond wire loop, making it one of the few capacitor technologies compatible with the thinnest AiP architectures.

• 0.15 mm (6 mil) profile: 3.3× thinner than 0402 MLCCs (0.50 mm), 2× thinner than 0201 MLCCs (0.30 mm). Total mounted height including 25 μm Au wire loop: <0.22 mm—compatible with 250 μm cavity depth.
• 15 mil footprint (0.14 mm²): 3.6× smaller than 0402 (0.50 mm²), enabling higher channel density in phased-array beamformer ICs. In a 256-element 28 GHz phased array, replacing 0402 MLCCs with 15 mil SLCs saves >90 mm² of interposer area—enough to integrate two additional beamformer ICs.
• Antenna-in-Package (AiP) ready: The single-sided bordered ceramic margin prevents epoxy bleed-out during die attach in tight AiP cavities where rework is impossible. The ultra-low 0.15 mm height is compatible with fan-out wafer-level packaging (FOWLP) and embedded die technologies where components are molded into the package substrate.
• 2.5D/3D heterogeneous integration: Compatible with silicon interposer, glass interposer, and organic substrate technologies. The fully-metallized bottom electrode provides maximum ground plane contact area for low-inductance RF grounding.

High Stability TCC & VCC — COG/NPO Zero-Drift mmWave Performance

At millimeter-wave frequencies, even tiny capacitance shifts produce large impedance changes. A ±15% capacitance variation (typical X7R over temperature) would shift the -j318 Ω reactance of a 10 pF capacitor at 50 GHz by ±48 Ω—completely changing the impedance match. The HACC100S15V500's COG/NPO dielectric eliminates these errors:

• TCC 0 ±30 ppm/°C: Total capacitance variation over -55°C to +125°C is ±0.3%—a reactance shift of <±1 Ω at 50 GHz. This is within the measurement uncertainty of a typical vector network analyzer calibration, meaning the capacitor's temperature dependence is below the noise floor of system-level RF calibration.
• VCC <10 ppm/V: At the full 50 V rated DC bias, the 10 pF capacitance changes by <0.05% (<0.005 pF). This is critical for direct-conversion and zero-IF receiver architectures where DC offsets appear across the DC blocking capacitor and any capacitance modulation produces AM-to-PM conversion—a nonlinear distortion mechanism that degrades EVM (Error Vector Magnitude) in high-order QAM modulation (64QAM, 256QAM) used in 5G NR.
• No aging, no microphonics, no piezoelectric effect: COG/NPO is non-ferroelectric and non-piezoelectric. It does not age (unlike X7R), does not generate voltage under vibration (unlike X7R/BaTiO3 which is strongly piezoelectric), and does not microphonic-couple mechanical vibration into phase noise—a critical advantage in vehicular and aerospace 5G platforms subjected to continuous vibration.

Comprehensive Parameter Datasheet

mmWave Performance Benchmarks: SLC vs. MLCC at 10 pF

Frequently Asked Questions

Q1: Why can't I use an 0201 or 0402 COG MLCC for mmWave DC blocking at 28 GHz?

The fundamental limitation is parasitic inductance (ESL), not capacitance value or dielectric quality. An 0402 MLCC with 10 pF COG dielectric has a self-resonant frequency (SRF) of approximately 4 GHz. At frequencies above SRF, the capacitor's impedance is dominated by its parasitic inductance—it behaves as an inductor, not a capacitor. At 28 GHz (7× above SRF), the MLCC presents an inductive impedance that blocks the RF signal rather than passing it. The HACC100S15V500's single-layer coaxial structure eliminates the internal electrodes and vias that create inductance in MLCCs, pushing the SRF to >45 GHz—well above all 5G mmWave bands. The physics is simple: shorter current path = lower inductance = higher SRF. An SLC's current path is 0.15 mm; an MLCC's is 2-5 mm through multiple electrodes and vias.

Q2: What is the insertion loss improvement from using HACC100S15V500 vs. wire-bonding a 10 pF MLCC at 39 GHz?

At 39 GHz, a wire-bonded 0402 10 pF MLCC presents an inductive impedance of approximately j86 Ω (from 350 pH ESL), acting as a series inductor rather than a coupling capacitor. The resulting insertion loss (S21) would be >3 dB—the MLCC is effectively blocking the signal rather than passing it. In contrast, the HACC100S15V500 at 39 GHz presents a capacitive impedance of -j408 Ω with <0.10 Ω ESR and <25 pH ESL—a nearly ideal series coupling element with S21 <0.05 dB. The difference is not incremental—it is the difference between a functional and non-functional design at mmWave frequencies.

Q3: How does the 0.15 mm profile enable Antenna-in-Package (AiP) integration compared to standard SMD capacitors?

5G mmWave AiP modules for handsets and small cells use a 3D stack: antenna substrate (top), air cavity (180-250 μm), active beamformer IC with embedded passives (bottom). The cavity height limits component Z-height to <200 μm after accounting for bond wire loop height. An 0402 MLCC at 500 μm simply cannot fit—it must be placed outside the cavity on the main PCB, adding 3-5 mm of 50 Ω trace (150-250 pH of additional parasitic inductance) between the DC block and the beamformer IC. The HACC100S15V500 at 150 μm height plus a 25 μm Au bond wire loop fits within a 200 μm cavity, enabling direct on-chip DC blocking with <100 μm interconnect distance—the shortest possible RF path with the lowest possible parasitic degradation.

S-Parameter Engineering & Assembly Guide

Epotek H20E Conductive Silver Epoxy SOP

• Adhesive: Epoxy Technology H20E, 2-5 nL per die using pneumatic micro-dispenser
• Placement: <50 gf collet force, compliant silicone tip, ±25 μm alignment
• Cure: 120°C / 30 min (standard) or 150°C / 15 min (fast-cure), ramp <10°C/sec
• Verification: Die shear test per industry-standard methods, >1.0 kgf minimum

Gold Wire Bonding Parameters

• Wire: 0.7-1.0 mil (18-25 μm) 99.99% Au
• Wedge bonding: 20-35 gf, 60-100 mW, 120-150°C stage, 20-50 ms
• Ball bonding: 15-30 gf, 40-80 mW, 150°C stage, 10-30 ms
• Clearance: Bond center ≥25 μm from Au electrode edge
• Inspection: 50× optical, reject >25% pad deformation or edge proximity violations

Flip-Chip Assembly for >50 GHz Operation

• UBM: Electroless Ni/Au or Cu UBM with SnAg solder bumps (contact factory)
• ESL reduction: Flip-chip reduces total ESL to <15 pH, extending SRF to >60 GHz
• Underfill: Capillary underfill with low-loss, low-Dk material (<3.2 @ 60 GHz)
• S-parameters: 2-port .s2p data (100 MHz-67 GHz) for both wire-bond and flip-chip configurations under NDA

To request S-parameter data, evaluation samples, or mmWave application support, contact our engineering team today.