HongAn Microwave Co., Ltd.
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| Brand Name: | Hoan |
| Model Number: | HACC101S20V101 |
| MOQ: | 10 |
| Payment Terms: | L/C,D/A,D/P,T/T,Western Union |
HACC101S20V101 Double-Sided Bordered SLC 100pF 100V (0.1-20GHz)
High-Frequency Technical Summary
The HACC101S20V101 is a high-performance, symmetrical Double-Sided Bordered Single Layer Ceramic Capacitor (SLC). This model is engineered for broadband DC blocking, RF coupling, and bypass filtering up to 20.0 GHz (covering UHF, L, S, C, X, Ku, and K microwave bands). With a stable 100 pF ± 20% capacitance, a compact 0.51 mm × 0.51 mm footprint, and a high-voltage rating of 100 V, this capacitor is highly suitable for high-density Tactical radar subassemblies, fiber-optic transceivers, and microwave hybrid microcircuits.
What sets the HACC101S20V101 apart is its symmetrical double-sided bordered architecture. Both the top and bottom electrodes feature a clean ceramic border margin. This symmetric structure eliminates top/bottom orientation requirements during pick-and-place, which significantly boosts automated assembly throughput and eliminates manual flipping errors.
Key Performance Advantages
•Symmetrical Double-Sided Border (DSB): Eliminates top-vs-bottom mounting orientation issues, enabling ultra-fast automated die attachment and picking.
•Dual-Side Epoxy Climb Protection: The ceramic border margins on both top and bottom electrodes act as a physical dam to stop conductive silver epoxy from climbing the sidewall, preventing short-circuits.
•Advanced Thin-Film Metallization System: Utilizes a highly robust TaN/TiW/Ni/Au thin-film stack on both faces, offering exceptional thermal stability, anti-migration protection, and resistance to solder leaching.
•100V Rated Voltage: Delivers higher voltage handling capacity in a miniature 20 mil × 20 mil (0.51 mm × 0.51 mm) footprint, maintaining low dielectric dissipation.
Overall Dimensions
Comprehensive Parameter Datasheet
| Specifications Category | Technical Parameter Name | Guaranteed Values | Testing/ Measurement Conditions |
| Electrical Specs | Nominal Capacitance | 100 | pF (+20% Tolerance @ 1kHz,1Vrms, 25°C) |
| Rated Working Voltage(DC) | 100 | V (Maximum continuous rating) | |
| Dissipation Factor (DF) | ≤1.5% | Tested at 1kHz, 1.0 Vrms, 25°C | |
| Insulation Resistance(IR) | ≥104MΩ | Tested at rated voltage DC, 25°C | |
| Recommended Frequency Band | 0.1-20.0 | GHz (Broadband Coupling andBypass Filtering) | |
| Physical Geometry | Outline Dimensions | 0.51x 0.51x 0.15 | mm (Length x Width x Height /20 x 20 x 6 mil) |
| Design Architecture | Double-Sided Bordered | Equal bare ceramic margin borders on both faces | |
| Metallization Stack | Top & Bottom Metallurgy | TaN/TiW/Ni/Au | Symmetrical thin-film stack on both surfaces |
| Outer Gold Thickness(Au) | ≥2.5 | um (Minimum thickness, wire-bond optimized) | |
| AssemblyProcesses | Mount Adhesion | Conductive Epoxy/Solder | Suitable for silver epoxy H20E /AuSn eutectic |
| Interconnect Connection | Gold Wire / Ribbon Bond | Thermosonic gold wire bonding compatible | |
| Reliability & Quality | Operating Temperature | -55 to +125 | ℃(Industrial & Tactical Grade) |
| Storage Temperature & RH | 20-25°C,40%-60% RH | Cleanroom environment | |
| Guaranteed Shelf Life | 1 | Year (Under optimal storage conditions) |
Symmetrical Thin-Film Metallization Stack Engineering
To ensure long-term reliability under Tactical-grade thermal cycling and high-humidity conditions, the HACC101S20V101 utilizes a symmetrical, vacuum-sputtered thin-film stack on both top and bottom:
| Metal Layer | Material | Standard Layer Thickness | Metallurgical Function & Engineering Value |
| Adhesion Layer | Tantalum Nitride (TaN) | Sputtered Base | Provides a highly stable, oxygen-blocking chemical bondto the ceramic substrate; prevents peeling under thermalstress. |
| Barrier Layer | Titanium-Tungsten (TiW) | Sputtered Barrier | Acts as a high-density diffusion barrier that preventsnickel and gold atoms from migrating into the ceramicdielectric. |
| Barrier Layer | Nickel (Ni) | Sputtered Sacrificial | Serves as a solder leach-resistant barrier; prevents goldleaching or scavenging during high-temperature solderreflow. |
| Bonding Finish | Gold (Au) | ≥2.5µm | Provides a highly conductive, oxide-free surfaceoptimized for both gold wire thermosonic bonding andsilver-filled epoxy attachment. |
Comparative Technical Matrix (HACC101S20V101 vs. Other SLC Designs)
This matrix compares the assembly and electrical performance of different single-layer ceramic capacitor designs:
| Engineering Parameter | Double-Sided Bordered (HACC101S20V101) | Single-Sided Bordered SLC | Standard Borderless SLC |
| Symmetry(Orientation) | Symmetrical. Top and bottomare identical. No flipping needed. | Asymmetric. Must verifytop/bottom side beforemounting. | Asymmetric. Must verifytop/bottom side before mounting. |
| Top Side Epoxy Safety | Outstanding. Bare ceramicmargin stops epoxy shortingtop surface. | Outstanding. Bareceramic margin stopsepoxy shorting topsurface. | Poor. Gold covers 100%of top, leading to highrisk of surface shorts. |
| Bottom Side Epoxy Safety | Outstanding. Exposed ceramicborder halts epoxy climb at thebase. | Moderate. Bottom goldcovers 100% of the base;epoxy climbs easily. | Poor. Solder/epoxy caneasily climb up the rawside walls. |
| Automated Assembly Speed | Maximum. High-speed pick-and-place with no visualorientation checking. | Medium. Automationrequires camerainspection to detect top/bottom. | Medium. Requires visionin spection to orientbefore placement. |
| Solder Leach Resistance | Excellent (Ni-Au Finish). | Moderate to Good (Depending on barrier). | Moderate to Good (Depending on barrier). |
S-Parameter Engineering & Sub-Millimeter Assembly Guide
To maximize high-frequency coupling and bypass efficiency while preventing mechanical damage, assembly engineers must adhere to the following guidelines:
Epotek H20E Conductive Silver Epoxy SOP
•Adhesive Specification: Use high-reliability, low-outgassing conductive silver epoxy (e.g., Epotek H20E).
•Dispensing Guidelines: Apply a microscopic dot of epoxy. Thanks to the bottom ceramic border on the HACC101S20V101, the epoxy is physically contained within the bonding pad, preventing short-circuits.
•Thermal Cure Profile: Cure at 120°C for 30 minutes (or alternatively 150°C for 15 minutes) with a slow-ramp cool-down to eliminate thermal shock on the ceramic substrate.
Gold Wire & Ribbon Bonding Constraints
•Bonding Method: Compatible with thermosonic gold wire bonding (ball-stitch or wedge-wedge) and gold ribbon bonding.
•Safe Bonding Clearance: The bonding wedge or capillary tip must land on the top gold pad at least 25 µm away from the electrode border edge. Bonding too close to the ceramic border will cause localized shearing forces, risking gold peeling or micro-cracks in the dielectric.
•Bonding Force: Control capillary pressure to prevent micro-fracturing the thin 0.15 mm ceramic wafer.
