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Ultra-Low Leakage 150pF 100V MOS Capacitor High Dielectric Breakdown Strength Extreme Thermal Endurance SLC Chip

Ultra-Low Leakage 150pF 100V MOS Capacitor High Dielectric Breakdown Strength Extreme Thermal Endurance SLC Chip

Brand Name: Hoan
Model Number: HACC151S100V200
MOQ: 10 Pieces
Payment Terms: L/C,D/A,D/P,T/T,Western Union
Detail Information
Place of Origin:
Shaanxi, China
Certification:
ISO 9001:2015, RoHS, REACH
Capacitance:
150pF ±10% (±5% Available)
Rated Voltage:
100V DC
Dielectric Withstanding Voltage:
>250V (250% Rated), 100% Production Tested
Leakage Current @ 25C:
<10nA At 100V DC
Leakage Current @ 200C:
<500nA At 100V DC
Maximum Operating Temperature:
200C Continuous
Dielectric Type:
Thermal SiO2, 300nm (high-temperature Stable)
TCC:
+35ppm/C (-55C To +200C)
Intrinsic Chip ESL:
<0.05nH
ESR @ 1GHz:
<0.1 Ohm
Q Factor @ 1MHz / @ 1GHz:
>2000 / >200
Chip Dimensions:
0.50 X 0.50 X 0.15 Mm
Top Metallization:
TiW-Au, 2.5um Au Min
Backside Metallization:
TiW-Pt-Au, 1.0um Au Min (Pt Diffusion Barrier)
Mounting Type:
Wire Bondable / AuSn Eutectic Or High-Temp Epoxy Die Attach
Operating Temperature:
-55C To +200C
Moisture Sensitivity:
MSL 1 (Unlimited Floor Life Per J-STD-020)
ESD Tolerance (HBM):
>2kV (Class 2 Per JESD22-A114)
Design Architecture:
Double-Sided Bordered (Margin)
Insulation Resistance:
≥10⁴ MΩ @ Rated Voltage DC, 25°C
Storage Temperature:
-65°C To +150°C
Substrate Resistivity:
>1000 Ohm·cm, Float-zone Silicon
Wire Bond Pull Strength:
>6 Gf For 25µm Au Wire (MIL-STD-883 Method 2011.7)
Dissipation Factor:
≤0.15% @ 1kHz, 1.0 Vrms
Highlight:

Ultra-Low Leakage MOS Capacitor 150pF

,

100V MOS Capacitor high dielectric strength

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SLC chip MOS Capacitor thermal endurance

Product Description

HACC151S100V200 Ultra-Low Leakage MOS Capacitor: 150pF 100V with High Dielectric Breakdown Strength and Extreme Thermal Endurance

The HACC151S100V200 is a 150pF ±10% single-layer MOS capacitor rated at 100V DC, engineered for continuous operation at temperatures up to 200°C. Fabricated on float-zone silicon (>1000Ω·cm) with 300nm thermally-grown SiO2 dielectric, this device delivers industry-leading <10nA leakage current at 25°C along with >250V dielectric withstanding voltage. Chip dimensions are 0.50 x 0.50 x 0.15mm with TiW-Au top metallization (2.5µm minimum Au) and TiW-Pt-Au backside (1.0µm minimum Au, Pt diffusion barrier).

1. Ultra-Low Leakage Current - Sub-Nanoampere Performance

Leakage current in MOS capacitors is dominated by trap-assisted tunneling through the SiO2 dielectric and surface leakage along the chip edges. The HACC151S100V200 minimizes both mechanisms through optimized thermal oxidation and advanced passivation:

  • Leakage at 25°C: <10nA at 100V DC - Exceptionally low compared to the industry-typical <10nA for equivalent-capacitance MOS capacitors. Achieved through ultra-low interface trap density from optimized dry oxidation with nitrogen annealing.
  • Leakage at 200°C: <500nA at 100V DC - Maintained low leakage even at the extreme 200°C operating temperature. The thermal SiO2 dielectric wide bandgap (8.9eV) provides inherent high-temperature leakage suppression.
  • Guard-ring edge passivation suppresses surface leakage currents along chip sidewalls, maintaining insulation integrity after 1000-hour HAST (130°C/85%RH) with less than 10% leakage degradation.

2. High Dielectric Breakdown Strength - 250% Margin for Mission-Critical Reliability

Dielectric breakdown is a leading field failure mechanism in high-voltage chip capacitors. The HACC151S100V200 eliminates this risk through conservative design margins:

  • Rated Voltage: 100V DC continuous - Suitable for GaN power amplifier drain bias networks (28-50V) with 2-3x headroom, high-voltage DC-DC converter filtering, and pulsed power energy storage.
  • Dielectric Withstanding Voltage (DWV): >250V DC (250% rated) - 100% production tested on every die with 5-second dwell. This 2.5x margin exceeds the standard 2x derating guideline recommended for high-reliability aerospace and defense applications.
  • Intrinsic Dielectric Strength: >10MV/cm - The 300nm thermal SiO2 provides uniform field distribution without the internal electrode edge concentration effects that limit MLCC breakdown voltage. TDDB lifetime exceeds 10 years at 125°C and rated voltage.

3. Extreme Thermal Endurance - Continuous Operation from -55°C to +200°C

Conventional MOS capacitors are rated to 125°C maximum. The HACC151S100V200 extends this by 75°C through materials engineering:

  • 200°C continuous operation - Qualified through 1000-hour HTOL at 200°C with 100V DC bias. Acceptance criteria: less than 2% capacitance shift, less than 2x initial leakage current. TiW diffusion barrier prevents Au-Si interdiffusion to >250°C, verified by Auger depth profiling.
  • TCC: +35ppm/°C across -55°C to +200°C - Capacitance variation below ±0.9% across the full 255°C temperature span.
  • AuSn eutectic recommended for >175°C - Conductive silver epoxy acceptable to 175°C; AuSn eutectic solder (280°C melting point) provides reliable die attach with zero degradation at 200°C.

Key Features

  • Ultra-Low Leakage: <10nA at 25°C/100V, <500nA at 200°C/100V - ideal for precision bias networks and charge-sensitive circuits
  • Insulation Resistance: ≥10⁴ MΩ at rated voltage — ensures reliable DC blocking in high-impedance circuits
  • Storage Temperature: -65°C to +150°C — wide non-operating temperature range supports logistics and storage in uncontrolled environments
  • High Breakdown Strength: >250V DWV (250% rated) with uniform field distribution - eliminates MLCC edge-concentration failure modes
  • Extreme Thermal Endurance: 200°C continuous operation, 1000-hour HTOL qualified with less than 2% parametric shift
  • SiO2 Dielectric Stability: Paraelectric with zero ferroelectric aging, near-zero dielectric absorption (<0.1%), and linear C-V characteristics
  • Harsh Environment Qualified: 100% wafer-level tested for capacitance, leakage, and breakdown; MSL 1 unlimited floor life

Electrical Specifications (T = 25°C unless noted)

Parameter Value Condition
Capacitance 150pF ±10% 1MHz, 1.0Vrms
Rated DC Voltage 100V Continuous
Dielectric Withstanding Voltage >250V DC 5 sec dwell, 100% test
Leakage Current @ 25°C <10nA 100V DC
Leakage Current @ 200°C <500nA 100V DC
TCC +35ppm/°C -55°C to +200°C
Q Factor @ 1MHz / @ 1GHz >2000 / >200 Typical
ESR @ 1GHz <0.1 Ohm De-embedded
Intrinsic Chip ESL <0.05nH De-embedded
Dielectric Absorption <0.1% 1kHz
ESD HBM >2kV JESD22-A114, Class 2
Dielectric Thermal SiO2, 300nm -
Chip Dimensions 0.50 x 0.50 x 0.15mm ±25µm
Operating Temp -55°C to +200°C Full parametric
RoHS Compliant EU 2015/863

Typical Applications

  • Downhole drilling and logging tools (150-200°C ambient) requiring DC blocking and bypass with stable parametric performance at formation temperatures
  • Aerospace engine monitoring electronics operating in uncooled engine bay environments
  • GaN-on-SiC power amplifier high-voltage drain bias decoupling (28-50V) with substantial voltage headroom
  • High-voltage DC-DC converter output filtering where leakage current directly impacts conversion efficiency
  • Industrial furnace and process control sensor electronics operating continuously at 175-200°C
  • Scientific instrumentation for high-temperature physics experiments requiring sub-nA leakage and stable capacitance

Assembly Quick Reference

Die Attach: AuSn eutectic solder (300-320°C, N2/H2 forming gas) for >175°C operation. Conductive Ag epoxy (Epotek H20E, 120°C/30min) acceptable to 175°C. AuGe or AuSi pre-forms for highest-temperature applications.

Wire Bonding: 25µm Au thermosonic ball bonding (120-150°C stage, 15-35gf force, >6gf pull strength). Al wedge bonding not recommended for continuous 200°C operation.

Storage: Waffle pack or gel-pak, vacuum-sealed with nitrogen purge. MSL 1 unlimited floor life at 30°C/85%RH.

Contact us today with your voltage, capacitance, and environmental requirements. Standard 150pF 100V evaluation samples ship within 2-3 weeks. Custom values from 10pF to 1000pF, voltage ratings up to 200V, and extended temperature qualification to 225°C available with 4-6 week prototyping lead time.