Superior Voltage Breakdown 1000pF 100V MOS Capacitor Stable Dielectric Wire Bondable Eutectic Chip

Superior Voltage Breakdown 1000 pF 100 V MOS Capacitor (HACC102S100V500) — Stable Dielectric, Wire-Bondable Eutectic Die Attach Chip

Summary: The Hoan HACC102S100V500 is a 1000 pF ±10% single-layer MOS capacitor rated at 100 V DC, with a dielectric withstanding voltage above 250 V DC (250% of the rated voltage), a stable 0 ±30 ppm/°C dielectric over -55°C to +125°C, and a metallisation system ready for both gold wire bonding and AuSn eutectic die attach.

What Is a Single-Layer MOS Capacitor?

A MOS capacitor (Metal–Oxide–Semiconductor capacitor) is a single-layer capacitor that uses a thermally grown silicon dioxide (SiO₂) dielectric on a high-resistivity silicon substrate, with metal electrodes on the top and bottom. With no internal electrode stack, current flows vertically through one dielectric layer, giving a near-zero intrinsic equivalent series inductance (ESL), a high self-resonant frequency (SRF) and predictable temperature behaviour compared with multilayer ceramic capacitors (MLCCs).

Key Performance Advantages

• Superior Voltage Breakdown — dielectric withstanding voltage greater than 250 V DC (250% of the 100 V continuous rating), 100% production tested per piece.
• Dielectric Stability — Class I COG/NPO-equivalent thermal SiO₂ with a temperature coefficient of 0 ±30 ppm/°C from -55°C to +125°C, a negligible DC-bias coefficient (<10 ppm/V) and no ferroelectric aging.
• Wire-Bondable & Eutectic Die Attach Ready — a top TiW-Au stack (≥2.5 µm Au) supports 25 µm gold wire bonding with >6 gf pull strength; the backside TiW-Pt-Au with a platinum diffusion barrier enables reliable AuSn (80/20) eutectic and conductive-epoxy die attach.
• Low Leakage — <10 nA at 25°C and <100 nA at 125°C at rated voltage.
• Low ESR — typically <0.1 Ω at 1 GHz for efficient RF bypass.

Electrical Specifications (T = 25°C unless noted)