| Brand Name: | Hoan |
| Model Number: | HACC221S15V500 |
| MOQ: | 10 Pieces |
| Payment Terms: | D/A,L/C,D/P,Western Union,T/T |
The HACC221S15V500 is a 220pF ±10% single-layer MOS capacitor rated at 15V DC, fabricated on float-zone silicon with 300nm thermal SiO2 dielectric. Chip dimensions are 0.50mm * 0.50mm * 0.15mm with TiW-Au top metallization and TiW-Pt-Au backside. The 220pF value provides three times the capacitance density of standard 100pF chips in the same footprint, enabling higher current handling and more effective low-frequency bypass in a single component.
The RF current-carrying capability of a bypass or coupling capacitor limits the maximum power that can be handled in a given circuit topology. The HACC221S15V500 is designed for circuits requiring both high capacitance and high current density in a compact footprint:
Component shelf life is a logistics concern for manufacturers maintaining inventory of critical components for long-lifecycle products. Many capacitor types have defined shelf life limitations due to material aging mechanisms. The HACC221S15V500 has no such limitations:
Despite the higher capacitance value (220pF vs. 100pF in the standard HACC101), the HACC221S15V500 maintains a high self-resonant frequency through the same low-inductance single-layer construction. With intrinsic chip ESL under 0.05nH, the chip-level SRF is approximately 1/(2π√(0.05*10⁻⁹ * 220*10⁻¹²)) ≈ 1.5GHz. In a practical assembly with a 0.5mm bond wire (~0.4nH total), the system SRF is approximately 1/(2π√(0.4*10⁻⁹ * 220*10⁻¹²)) ≈ 540MHz—still adequate for bypass applications through UHF and into lower L-band frequencies. Where higher SRF is required, the same parallel-bond-wire techniques described for the 100pF variant apply, with approximately √(220/100) ≈ 1.48* lower SRF at any given inductance due to the higher capacitance.
| Parameter | Value | Condition |
| Capacitance | 220pF ±10% | 1MHz, 1.0Vrms |
| Available Tolerances | ±10% (K), ±5% (J) | — |
| Rated DC Voltage | 15V | Continuous |
| Dielectric Strength | >75V DC | 1 min, 25°C |
| Intrinsic Chip ESL | <0.05nH | De-embedded |
| Chip-Level SRF | >1.5GHz | 220pF, no bond wire |
| System SRF (0.5mm bond wire) | >540MHz | Single 25µm Au wire |
| Q Factor @ 1MHz / @ 1GHz | >2000 / >250 | Typical |
| ESR @ 1GHz | <0.1Ω | Typical |
| Leakage @ 25°C / @ 125°C | <10nA / <100nA | 15V DC |
| TCC | +35ppm/°C | -55°C to +125°C |
| Dielectric Aging Rate | 0% per decade-hour | Amorphous SiO2, no ferroelectric domains |
| Storage Life (25°C, 50%RH) | Unlimited | No degradation mechanism |
| Max RMS Current (2 bond wires) | 1.5A | ΔTJ < 20°C, θJC < 30 K/W |
| Capacitance Density | 880pF/mm² | 220pF in 0.25mm² |
| Dielectric | Thermal SiO2, 300nm | — |
| Substrate | Float-zone Si, >1000Ω·cm | — |
| Chip Dimensions | 0.50 * 0.50 * 0.15mm | ±0.025mm |
| Top / Backside Metallization | TiW+Au 2.5µm / TiW-Pt-Au 1.0µm | — |
| Operating / Storage Temp | -55 to +125°C / -65 to +150°C | — |
| RoHS | Compliant (EU 2015/863) | — |
| Aspect | HACC221S15V500 | X7R MLCC (typical) |
| Capacitance aging | 0% per decade-hour | 3-5% per decade-hour |
| Moisture sensitivity | MSL 1, unlimited floor life | MSL 2-3, floor life 1 week-168 hours |
| Solderability shelf life | Unlimited (Au surface) | 12-24 months (Sn or SnPb finish) |
| Requalification after storage | Not required | Recommended after 2+ years |
| Recommended storage | ESD-safe containers, ambient | Dry-pack, humidity indicator required |
Standard product ships as 0.50mm * 0.50mm chips in anti-static waffle packs with vacuum-sealed moisture barrier bag outer packaging. No special storage conditions are required—the MSL 1 rating permits unlimited floor life at standard factory ambient conditions (≤30°C, ≤85%RH). For programs planning single large-quantity procurements, contact us to discuss lot reservation and extended delivery schedules to align with your production ramp.
Contact us for current density derating data, shelf-life certification letters for your quality system, or volume pricing for multi-year procurement agreements.