HACC102S25V810 MOS Capacitors 1000 pF 25V 8 Bit Binary Weighted Taps Ultra Low Dielectric Absorption

HACC102S25V810 MOS Capacitor 1000 pF 25 V 8-Bit Binary-Weighted Precision Tuning with Zero Piezoelectric Noise

Model: HACC102S25V810
Product name: Precision-signal single-layer MOS capacitor, 8-bit binary-weighted multi-tap, 1000 pF ±1%, 25 V DC
Product category: MOS Capacitors — wire-bondable single-layer chip (SLC)
Brand: Hoan  |  Place of origin: Shaanxi, China  |  Certification: ISO 9001:2015, RoHS 2015/863, REACH
Model coding: HACC + capacitance code (102 = 10 × 10² pF = 1000 pF) + S = single layer + rated voltage + V + lot series
Also searched as: MOS capacitor, MIS capacitor, single-layer capacitor (SLC), single-layer ceramic capacitor, wire-bondable chip capacitor, bare-die capacitor, precision trim capacitor

Definition. The HACC102S25V810 is a wire-bondable single-layer MOS capacitor die built on high-resistivity float-zone silicon (>1000 Ω·cm) with a 300 nm thermally grown SiO₂ dielectric. It delivers 1000 pF ±1% at 25 V DC in a 1.20 x 1.20 x 0.20 mm die, and carries eight laser-trimmed binary-weighted tap pads (3.9 pF LSB, 256 selectable values) so the final capacitance can be set in-circuit after die attach and bonding.

Actual product: 1.20 x 1.20 x 0.20 mm die. Top electrode TaN/TiW/Ni/Au (≥2.5 µm Au) with one main pad plus eight binary-weighted tap pads; full backside TiW-Pt-Au ground plane; un-metallized ceramic margin acts as an epoxy stop and as an optical reference for the bonder.

Key facts at a glance

• 1000 pF ±1% nominal, 8-bit binary-weighted taps, LSB 3.9 pF, 256 monotonic settings on one die
• Dielectric absorption <0.02% and piezoelectric charge output <2 µV per volt of bias
• 25 V DC rated, DWV >75 V (300% of rated), TCC 0 ±30 ppm/°C from -55 °C to +125 °C
• Q >2000 at 1 MHz, intrinsic ESL <0.05 nH, leakage <10 nA, MSL 1
• Tolerance, tap count, voltage and footprint are customisable; standard stock ships in 5-7 working days

Zero piezoelectric noise and dielectric absorption below 0.02%

Silicon dioxide is amorphous and paraelectric: it has no ferroelectric domains and no piezoelectric axis. Mechanical stress therefore generates no charge, and electrical stress generates no dimensional change. In a measurement chain this shows up in three ways:

• No vibration-induced voltage. A biased part held in a 20 g sine sweep from 10 Hz to 2000 Hz stays below 2 µV per volt of bias (MIL-STD-810H Method 514.8). Class II ceramic capacitors of similar value typically deliver 10-100 mV under the same excitation, which is enough to corrupt a 16-bit conversion window.
• Dielectric absorption below 0.02%. Measured with a 60 s charge / 60 s discharge cycle at 1 kHz, 1.0 Vrms, the recovered charge is less than one fifth of a 0.1% part. In sample-and-hold amplifiers, charge-redistribution DACs, peak detectors and precision integrators this removes the repeatable settling tail that is usually corrected in firmware.
• No ageing, no DC-bias loss. VCC is below 10 ppm/V, so the value trimmed at 0 V is the value at 25 V full bias, and calibration done at final test stays valid for the life of the assembly.

Binary-weighted taps for on-chip precision tuning

The eight taps use binary area ratios and are laser-trimmed on wafer, so each tap is a calibrated increment rather than a nominal one:

• Trim after assembly. Bond the main pad, measure the circuit in situ, then bond only the tap combination that lands the value on target. Die-attach adhesive thickness, bond-wire length and carrier parasitics are absorbed by the trim instead of by the tolerance budget.
• Monotonic by construction. Tap-to-tap matching of ±0.5% gives DNL below 0.5 LSB and INL below 1 LSB across the full 8-bit range — no missing codes, unlike switched-capacitor trim banks with capacitor ratio mismatch.
• Fewer parts, fewer attach steps. One binary-weighted die replaces up to eight discrete trim capacitors, eight die-attach operations and their accumulated tolerance stack.

Where it is used

• Precision instrumentation and strain-gauge / photodiode front-end filters
• Sample-and-hold buffers and ADC driver networks where settling accuracy matters
• On-die or hybrid-microcircuit trim of active filters, oscillators and reference networks
• RF and microwave coupling, bypass and matching in hybrid modules and T/R hybrids
• Sensor signal conditioning in vibration-rich environments (motion stages, pumps, vehicle-mounted electronics)
• Channel-matched capacitor banks in multi-channel data acquisition

Selection guide: single-layer MOS vs Class II (X7R) MLCC

Requesting a quotation — what we need from you

To quote and, where needed, design a custom variant, send: target capacitance and tolerance, rated DC voltage, required tap count or tuning resolution, chip footprint limit, attach method (epoxy, AuSn, sintered silver), wire type and diameter, annual quantity, and the documentation package you need. Standard 1000 pF / 25 V parts ship in 5-7 working days; custom configurations are quoted within 2 working days and built in 3-4 weeks.

Datasheet revision A.1. Typical values are design-characterisation data, not guaranteed limits; guaranteed limits are the specification table and the lot test report. Specifications may be updated without notice — confirm critical parameters with the sales engineer before design freeze.