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HACC471S100V900 MOS Capacitors 470 pF 100V ESD Hardened Die Surge Tolerant SiC GaN CMOS Compatible

Name: HACC471S100V900 MOS Capacitors 470 pF 100V ESD Hardened Die Surge Tolerant SiC GaN CMOS Compatible
Brand: HongAn Microwave Co., Ltd.
SKU: HACC471S100V900
Price: Negotiable USD
Availability: InStock

Brand Name:	Hoan
Model Number:	HACC471S100V900
MOQ:	10 Pieces
Payment Terms:	T/T,L/C,D/A,D/P

Detail Information

Product Description

Detail Information

Place of Origin:

Shaanxi, China

Certification:

ISO 9001:2015

Q Factor At 1 MHz:

Typical 1500, Minimum 1000

ESR At 1 GHz:

Typical 0.15 Ohm, Maximum 0.20 Ohm (de-embedded)

Intrinsic ESL:

<0.06 NH

Die Size:

0.90 X 0.90 X 0.20 Mm (+/-25 Um)

Substrate:

Float-zone Silicon >1000 Ohm-cm

Wire Bond Pull Strength:

>6 Gf For 25 Um Au Wire, MIL-STD-883 Method 2011.7

Operating Temperature:

-55 C To +125 C

Highlight:

MOS Capacitors 470 pF 100V

ESD Hardened MOS Capacitors

Surge Tolerant SiC GaN Capacitors

Product Description

Photo: HACC471S100V900 single layer MOS capacitor die, 0.90 mm square, passivated top pad and backside plane

HACC471S100V900

470 pF MOS Capacitor, 100 V, ESD Hardened Die, Surge Tolerant, SiC GaN and CMOS Compatible

Single layer MOS capacitor with passivated dielectric and selectable gold or gold-free metallisation for wide-bandgap and CMOS assembly flows

470 pF ±5%100 V DCDWV >250 VSurge 8/20 µs, 5 A peakAu or Au-free backside0.90 × 0.90 × 0.20 mm

Key Facts at a Glance

Item	Value
Model	HACC471S100V900
Product type	Single layer MOS capacitor (single layer ceramic capacitor, SLC, wire bondable chip capacitor)
Category	MOS Capacitors
Capacitance	470 pF ±5% at 1 MHz, 1.0 Vrms, 25 °C
Rated voltage	100 V DC continuous; dielectric withstanding voltage >250 V DC
Dielectric	Thermal SiO2, approx. 400 nm, passivated, on float-zone silicon >1000 Ω·cm
Q factor	Typical 1500 at 1 MHz; minimum 1000
Temperature coefficient	0 ±30 ppm/°C over −55 °C to +125 °C
Die size	0.90 × 0.90 × 0.20 mm, ±25 µm
Metallisation	Top TiW/Ni/Au ≥2.5 µm Au (Al option); backside TiW-Pt-Au ≥1.0 µm Au or gold-free TiW/Al
Mounting method	Bare die: conductive epoxy, eutectic or sintered attach, then wire bonding. Not a reflow soldered SMT part.
Brand / origin	Hoan / Shaanxi, China
Certification	ISO 9001:2015
Minimum order	10 pieces
Delivery	1–2 weeks for standard stock, 3–4 weeks for custom production

What This Component Is

The HACC471S100V900 is a 470 pF, 100 V single layer MOS capacitor built on the same vertical metal-oxide-semiconductor structure as the rest of the range: a gold top pad, a thermally grown silicon dioxide dielectric of about 400 nm, and a float-zone silicon substrate that forms the backside electrode. The thicker oxide is what supports the 100 V rating and the 250% withstanding voltage margin. The die is passivated and uses a field plate geometry that moves the peak electric field away from the electrode edge, which is the location where partial discharge and handling damage usually begin. It is supplied as bare die for die attach and wire bonding, and it is offered with either a gold or a gold-free metallisation so that the same die design can enter a wide-bandgap module line or a CMOS line without a second qualification cycle.

ESD Response and Surge Pulse Capability

Single layer capacitors are thin-oxide devices and no vendor can make a bare die immune to electrostatic discharge. What can be engineered, and what is stated here, is a hardened construction plus measured pulse capability, with the limits written down so that they can be designed around.

Stress	Rating	Condition
Dielectric withstanding voltage	>250 V DC (250% of rated)	5 s dwell, 1 mA trip, production tested on every die
ESD classification, human body model	Class 0 (0–250 V) per JESD22-A114	Bare die classification; passivation and field plate geometry raise the survival margin in handling but do not replace ESD control
ESD, machine model	≥100 V	JESD22-A115, design target, verified per lot on request
Surge pulse, 8/20 µs waveform	5 A peak, 10 pulses	Combination wave generator, 2 Ω source impedance, 60 s between pulses; capacitance change <0.5% and insulation resistance >10⁴ MΩ after stress
Repetitive pulse current	1 A, 10⁵ cycles	1 µs square pulse at 1 kHz, 25 °C, capacitance drift <0.2%
Transient overvoltage	200 V, 1 ms, 100 shots	Clamped inductive load, capacitance change <0.5%

What this does not mean: the part is not a protective device. It must be assembled in an ESD protected area, and a sensitive node still needs its own system protection such as series impedance, a clamp or a transient suppressor. The surge ratings apply to the die bonded with wire of 1.0 mm or shorter; longer wires and long traces in front of the node raise the real stress and must be qualified at system level.

Full Parameter Table

Parameter	Value	Tolerance	Test condition / method
Nominal capacitance	470 pF	±5%	1 MHz, 1.0 Vrms, 25 °C, four-terminal pair, Keysight E4990A
Rated DC voltage	100 V DC continuous	—	−55 °C to +125 °C
Dielectric withstanding voltage	>250 V DC (250% of rated)	tested on every die	5 s dwell, 1 mA trip limit, 25 °C
Q factor at 1 MHz	Typ. 1500 / min. 1000	—	1 MHz, 1.0 Vrms, 25 °C
ESR at 1 GHz	Typ. 0.15 Ω / max. 0.20 Ω	—	2-port shunt-through, de-embedded to die pads
Intrinsic ESL	<0.06 nH	max.	De-embedded from S-parameters, 1–3 GHz
Self-resonant frequency	>1.5 GHz chip only; >700 MHz with 1.0 mm Au wire	min.	S21 zero-phase crossing, 25 °C
Dissipation factor	≤0.15%	max.	1 kHz, 1.0 Vrms, 25 °C
Temperature coefficient	0 ±30 ppm/°C	±30 ppm/°C	−55 °C to +125 °C, 10 °C steps, 30 min soak
DC bias coefficient	<10 ppm/V	max.	0–100 V, 10 V steps, 25 °C
Leakage current	<10 nA at 25 °C; <100 nA at 125 °C	max.	100 V DC, 60 s electrification
Insulation resistance	≥10⁴ MΩ	min.	100 V DC, 60 s, 25 °C
ESD classification	Class 0 HBM (0–250 V); MM ≥100 V	—	JESD22-A114 and JESD22-A115, bare die
Surge capability	5 A peak, 8/20 µs, 10 pulses	—	Combination wave generator, 2 Ω source, capacitance change <0.5%
Die size	0.90 × 0.90 × 0.20 mm	±25 µm	Optical measurement, per wafer lot
Substrate resistivity	>1000 Ω·cm float-zone silicon	min.	4-point probe, per lot
Dielectric thickness	approx. 400 nm thermal SiO2	±5%	Ellipsometry, per lot
Top metallisation	TiW/Ni/Au, ≥2.5 µm Au (Al option)	min. Au	XRF and cross-section, per lot
Backside metallisation	TiW-Pt-Au ≥1.0 µm Au, or gold-free TiW/Al	min. Au	XRF, per lot
Electrode architecture	Double-sided bordered margin, passivated	—	Visual, every die
Thermal budget	Capacitance change <0.5% after 350 °C / 30 min	max.	Nitrogen ambient, measured before and after anneal
Wire bond pull strength	>6 gf for 25 µm Au wire	min.	MIL-STD-883 Method 2011.7, per lot
Operating temperature	−55 °C to +125 °C	—	Full parametric compliance over range
Moisture sensitivity	MSL 1	—	J-STD-020, unlimited floor life at ≤30 °C / 85% RH
Restricted substances	Lead free, halogen free, beryllium oxide free	—	EU 2015/863, IEC 61249-2-21, REACH SVHC list

Assembly Instructions for HACC471S100V900

Bare die, die attach plus wire bonding. This is not a reflow soldered SMT component. The part carries a gold or aluminium thin-film backside for conductive epoxy, eutectic or sintered attach, and a gold or aluminium top pad for wire bonding. It has no solderable terminations and must not be reflowed, wave soldered, or described as a reflow compatible capacitor.

Orientation

The metallised top pad faces up; the full backside plane faces the carrier. The ceramic margin is visible on both faces and is the vision reference for pick and place.
The die is square with a symmetric border and has no corner key, so orientation must be read from the bond pad face at 20–40× before dispensing.
A flipped die produces a capacitive short after cure and cannot be reworked; treat orientation check as a mandatory in-process step.

Typical Applications

DC link and bias decoupling in SiC and GaN power stages where the bias rail reaches 100 V
Gate loop and snubber networks requiring capacitance that does not shift with bias
RF power amplifier drain bias networks in GaN-on-SiC modules
High voltage DC blocking in bias tees and test fixtures
Filtering and charge storage in hybrid microcircuits and multi-chip modules
Industrial power conversion, motor drive sensing and instrumentation front ends
Automotive sensor and radar modules built on wide-bandgap devices

HACC471S100V900 · MOS Capacitors · Brand: Hoan · Shaanxi, China · ISO 9001:2015 · Datasheet revision 2.0
Ordering code example: HACC + capacitance code (471 = 470 pF) + S + rated voltage (100 V) + die code (900 = 0.90 mm).
For surge retention reports, the gold-free metallisation process note, or evaluation samples matched to your bias rail, contact our engineering desk.

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