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HACC103S50V910 MOS Capacitors 10000 pF 50V Ultra Broadband Flat Impedance TID Qualified 100 krad

HACC103S50V910 MOS Capacitors 10000 pF 50V Ultra Broadband Flat Impedance TID Qualified 100 krad

Brand Name: Hoan
Model Number: HACC103S50V910
MOQ: 10 Pieces
Payment Terms: T/T,L/C,D/P,D/A
Detail Information
Place of Origin:
Shaanxi, China
Certification:
ISO 9001:2015, RoHS 2015
Impedance Magnitude:
0.05-0.30 Ω From 10 MHz To 40 GHz
Impedance Flatness:
±1.5 DB, No Anti-resonance Below 20 GHz
Rated Voltage:
50 V DC (DWV >150 V, 300% Of Rated)
Total Ionizing Dose:
100 Krad(Si) Functional, 200 Krad(Si) Survival
Capacitance Shift After TID:
<2% @ 100 Krad(Si)
Low Dose Rate Sensitivity:
<3% Shift At 10 Mrad(Si)/s
Chip Dimensions:
1.50 × 1.50 × 0.25 Mm (±25 µm)
Highlight:

Ultra Broadband Flat Impedance Decoupling

,

TID Qualified 100 krad Capacitor

,

10000 pF Flat Impedance Chip

Product Description

HACC103S50V910 MOS Capacitor 10 nF 50 V Ultra-Broadband Flat Impedance, Total-Dose Qualified to 100 krad(Si)

Model: HACC103S50V910
Product name: Ultra-broadband power-decoupling single-layer MOS capacitor, 10 nF ±5%, 50 V DC, total-ionizing-dose qualified
Product category: MOS Capacitors — wire-bondable single-layer chip (SLC), high-reliability series
Brand: Hoan  |  Place of origin: Shaanxi, China  |  Certification: ISO 9001:2015, RoHS 2015/863, REACH, ASTM E595 tested
Model coding: HACC + capacitance code (103 = 10 × 10³ pF = 10 nF) + S = single layer + rated voltage + V + lot series
Also searched as: MOS capacitor, MIS capacitor, single-layer capacitor (SLC), wire-bondable decoupling capacitor, broadband bypass capacitor, high-reliability ceramic capacitor

Definition. The HACC103S50V910 is a wire-bondable single-layer MOS capacitor die on high-resistivity float-zone silicon with a 300 nm thermally grown SiO₂ dielectric. It provides 10 nF ±5% at 50 V DC in a 1.50 x 1.50 x 0.25 mm die, keeps impedance between 0.05 and 0.30 Ω from 10 MHz to 40 GHz without an anti-resonance peak, and is qualified to 100 krad(Si) total ionizing dose for long-life, high-reliability platforms.


HACC103S50V910 MOS capacitor die 1.50 x 1.50 x 0.25 mm with wide gold bond pad regions for parallel wire bonding

Actual product: 1.50 x 1.50 x 0.25 mm die. Large-area top electrode with two wide bond-pad regions for two to four parallel 25 µm Au bonds; full backside TiW-Pt-Au ground plane; outgassing tested to ASTM E595.


Full specification table

All values at 1 MHz, 1.0 Vrms, 25 °C unless a different test condition is stated.

Parameter Value Tolerance Test Condition
Nominal capacitance 10 000 pF (10 nF) ±5% 1 MHz, 1.0 Vrms, 25 °C, four-terminal pair
Impedance magnitude |Z| 0.05 - 0.30 Ω ±15% unit-to-unit 10 MHz to 40 GHz, de-embedded to die terminals
Impedance flatness ±1.5 dB max deviation 10 MHz to 40 GHz, no anti-resonance below 20 GHz
Rated DC voltage 50 V DC continuous -55 °C to +125 °C
Dielectric withstanding voltage >150 V DC >300% of rated 5 s dwell, 100% production test, 25 °C
Total ionizing dose (TID) 100 krad(Si) functional, 200 krad(Si) survival - Co-60, 50-300 rad(Si)/s, biased 50 V, MIL-STD-883 Method 1019 Condition A, 24 h rebound
Capacitance shift after 100 krad(Si) <2% max 1 MHz, 25 °C, biased irradiation
Leakage after 100 krad(Si) <50 nA max 50 V DC, 25 °C
Low-dose-rate sensitivity <3% shift max 10 mrad(Si)/s to 100 krad(Si), biased, 25 °C
Single-event behaviour no active junction in the conduction path - Passive dielectric; SEL / SEU / SEGR mechanisms do not apply
TCC 0 ±30 ppm/°C -55 °C to +125 °C 1 MHz, 25 °C reference
VCC (DC bias coefficient) <10 ppm/V max 0 V to 50 V DC
Dissipation factor ≤0.15% max 1 kHz, 1.0 Vrms, 25 °C
ESR <0.05 Ω at 1 GHz max 2-port S-parameter, de-embedded
Intrinsic ESL <0.04 nH max De-embedded, 1-40 GHz
Insulation resistance ≥10⁴ MΩ min 50 V DC, 60 s electrification
Leakage current <10 nA at 25 °C, <100 nA at 125 °C max 50 V DC, 60 s
ESD rating Class 0 (HBM) - JESD22-A114
Chip dimensions 1.50 x 1.50 x 0.25 mm ±25 µm Optical CMM, lot sample
Substrate / dielectric Float-zone Si >1000 Ω·cm / 300 nm thermal SiO₂ - Wafer-level process control, CpK >1.33
Top / backside metallization TaN/TiW/Ni/Au ≥2.5 µm Au / TiW-Pt-Au ≥1.0 µm Au - Pull test per MIL-STD-883 Method 2011.7
Outgassing TML <0.30%, CVCM <0.05% max ASTM E595, 125 °C, 24 h vacuum
Wire bond pull strength >6 gf min 25 µm Au wire, MIL-STD-883 Method 2011.7
Thermal cycling 500 cycles, -55 °C to +125 °C no parametric drift beyond spec 10 °C/min, monitored per 100 cycles
Moisture sensitivity MSL 1 - J-STD-020, unlimited floor life


Documentation supplied with each order

  • Certificate of conformance and lot traceability report
  • DC parametric test report (capacitance, DWV, leakage, insulation resistance)
  • RF test report with S-parameter files, 10 MHz to 40 GHz on request
  • Total ionizing dose test report with Co-60 dosimetry and measurement points
  • Outgassing report per ASTM E595 and thermal-cycling summary
  • Wafer map with die coordinates; RoHS 2015/863 and REACH declarations


Assembly instructions — HACC103S50V910

Orientation. Top electrode faces up, with the two wide bond-pad regions on opposite edges; the whole backside is the ground plane and must be attached face-down to the carrier ground. The die is square but the metallization is not symmetric, so confirm pad orientation with the bonder vision system before dispensing adhesive.

Die attach — conductive epoxy or AuSn eutectic, not solder reflow. Conductive silver epoxy with a 20-35 µm bond line, cured 120 °C for 30 min or 150 °C for 15 min in nitrogen; or AuSn 80/20 eutectic at 300-320 °C in N₂/H₂ forming gas. For lowest impedance above 20 GHz use the thinnest qualified bond line, because adhesive thickness sets the ground-return inductance. This model is a wire-bondable bare die qualified for epoxy or eutectic attach; the solderable and reflow-solder variants are separate models with separate assembly drawings, and a solder reflow profile must not be substituted for the qualified cure schedule.

Adhesive dispense. Dot or cross pattern covering 60-80% of the die footprint, centred, with the fillet stopped by the un-metallized margin. Avoid voids: a 1 mm² void adds several nanohenries to the ground return. Cure in a nitrogen oven with a 2 °C/min ramp to prevent outgassing bubbles.

Wire bonding. Two to four parallel 25 µm Au thermosonic ball bonds per pad region, stage 120-150 °C, 15-35 gf, 40-80 mW ultrasonic, pull >6 gf per bond; 25-33 µm Al ultrasonic wedge bonding is also supported at 25 °C. Keep loop length under 0.5 mm and loop height under 150 µm, and land bonds at least 25 µm inside the pad edge. Use all four bond positions for rails carrying more than 1 A RMS.

Cleaning and storage. No aqueous cleaning after bonding. IPA only for residue from neighbouring parts, 60 s maximum, air dry; do not ultrasonic-clean bonded dies. Store in waffle pack or gel-pak in a nitrogen cabinet at 20-25 °C, 40-60% RH. MSL 1, unlimited floor life; handle as ESD class 0 (HBM).


Requesting a quotation — what we need from you

To quote or to configure a custom version, send: capacitance and tolerance, rated DC voltage, impedance target and frequency band, chip footprint limit, required total-dose envelope, attach method, bond count and wire diameter, annual quantity, and the documentation package you need. Standard 10 nF / 50 V parts ship in 2-3 weeks with the total-dose report; custom configurations are quoted within 2 working days.

Datasheet revision A.1. Typical values are design-characterisation data, not guaranteed limits; guaranteed limits are the specification table and the lot test report. Total-dose data applies to the stated dose-rate range only. Specifications may be updated without notice — confirm critical parameters before design freeze.