Ultra Low Total Harmonic Distortion MOS Capacitors Zero Dielectric Dispersion 100 pF 50V Single Layer Chip For Analog

HACC101S50V601 100pF 50V MOS Capacitor Ultra Low Total Harmonic Distortion Zero Dielectric Dispersion Paraelectric SiO2 Single Layer Chip

The HACC101S50V601 is a 100pF ±10% single-layer MOS capacitor rated at 50V DC, fabricated on float-zone silicon (>1000 Ω·cm) with an amorphous paraelectric thermal SiO₂ dielectric and TiW-Au / TiW-Pt-Au metallization. Standard chip dimensions are 0.50mm × 0.50mm × 0.15mm (±25µm). Because thermal SiO₂ is paraelectric (no ferroelectric domains), the device exhibits an ultra-linear capacitance-versus-voltage characteristic and a frequency-independent permittivity, making it suitable for precision analog and mixed-signal circuits where capacitor-induced distortion and value shift cannot be tolerated.

Ultra-Low Total Harmonic Distortion for Analog Signal Paths

Any voltage-dependent capacitance modulates the signal passing through it and generates harmonic distortion. Ferroelectric ceramic dielectrics (X7R, X5R classes) change value by 30-80% under DC bias and therefore distort analog signals measurably. The paraelectric SiO₂ dielectric of the HACC101S50V601 has no ferroelectric domains and keeps the capacitance virtually constant versus bias voltage:

• Ultra-linear CV characteristic: Capacitance change from 0V to the full 50V rating is below 0.05% (voltage coefficient <10 ppm/V), so the device adds no measurable C(V) nonlinearity to the signal path.
• Low dissipation factor: ≤0.15% at 1kHz (1.0Vrms) and tanδ <0.001 at 1GHz, keeping resistive losses far below the level that would affect distortion or noise performance in precision circuits.
• Low dielectric absorption: <0.1% at 1kHz. The dielectric stores negligible charge memory, so sample-and-hold circuits, integrators, and precision filters recover to true zero without voltage-error residue.
• No aging drift: The paraelectric dielectric has no ferroelectric domain relaxation, so capacitance does not decay with time and does not require aging compensation in long-life instrumentation.

Electrical Characteristics and Reliability

• Capacitance: 100pF ±10% (±5% available on custom orders)
• Temperature coefficient (TCC): +35 ppm/°C over -55°C to +125°C
• Q factor: >2000 at 1MHz, >300 at 1GHz
• ESR at 1GHz: <0.08Ω; intrinsic chip ESL: <0.05nH (de-embedded)
• SRF: >10GHz chip-level (de-embedded); >1.5GHz with 0.5mm Au bond wire
• Leakage current: <10nA at 25°C at 50V DC; insulation resistance ≥10⁴ MΩ at rated voltage, 25°C
• Wire bond pull strength: >6gf for 25µm Au wire (MIL-STD-883 Method 2011.7)
• Moisture sensitivity: MSL 1 (unlimited floor life per J-STD-020)
• ESD rating: Class 0 (HBM) per JESD22-A114 — handle with standard ESD precautions
• Operating temperature: -55°C to +125°C; storage: -65°C to +150°C
• Testing: 100% die tested per wafer lot (capacitance, DF, leakage, DWV), KGD wafer map available

Typical Applications

Precision analog and mixed-signal circuits: high-end audio signal paths, ADC/DAC reference decoupling and anti-alias filtering, active filters and equalizers, sample-and-hold circuits, precision instrumentation, servo and measurement systems, and wideband analog front ends that span audio through microwave frequencies.